Editing MIPS architecture (section)

== Design ==
{{expand section|date=February 2020}}

MIPS is a modular architecture supporting up to four [[coprocessor]]s (CP0/1/2/3). In MIPS terminology, CP0 is the System Control Coprocessor (an essential part of the processor that is implementation-defined in MIPS I–V), CP1 is an optional [[floating-point unit]] (FPU) and CP2/3 are optional implementation-defined coprocessors (MIPS III removed CP3 and reused its opcodes for other purposes). For example, in the [[PlayStation (console)|PlayStation]] video game console, CP2 is the [[PlayStation technical specifications#Central processing unit (CPU)|Geometry Transformation Engine]] (GTE), which accelerates the processing of geometry in 3D computer graphics.