Editing Intel i860 (section)

==Technical features==
The i860 combined a number of features that were unique at the time, most notably its [[very long instruction word]] (VLIW) architecture and powerful support for high-speed floating-point operations.<ref>{{cite journal
 |last1=Kohn
 |first1=Les
 |last2=Margulis
 |first2=N.
 |title=Introducing the Intel i860 64-Bit Microprocessor
 |pages=15–30
 |journal=IEEE Micro
 |publisher=IEEE Computer Society
 |date=August 1989
 |volume=9
 |issue=4
 |doi=10.1109/40.31485
 |s2cid=21922034
 }}</ref> The design uses two classes of instructions: "core" instructions which use a [[32-bit]] [[Arithmetic logic unit|ALU]], and "floating-point or graphics" instructions which operate on a floating-point adder, a floating-point multiplier, or a 64-bit integer graphics unit. The system had separate [[Instruction pipelining|pipelines]] for the ALU, floating-point adder, floating-point multiplier, and graphics unit. It can [[Instruction cycle|fetch and decode]] one "core" instruction and one "floating-point or graphics" instruction per clock. When using dual-operation floating-point instructions (which transfer values between subsequent dual-operation instructions), it is able to execute up to three operations (one ALU, one floating-point multiply, and one floating-point add-or-subtract) per clock.<ref name=":0" /><ref name=":1">{{Cite book |url=http://www.bitsavers.org/components/intel/i860/240329-002_i860_64-Bit_Microprocessor_Programmers_Reference_Feb89.pdf |title=i860 64-bit Microprocessor Programmer's Reference Manual |publisher=[[Intel]] |year=1989 |location=Santa Clara, CA, USA |language=en |archive-url=https://web.archive.org/web/20220223123909/http://bitsavers.org/components/intel/i860/240329-002_i860_64-Bit_Microprocessor_Programmers_Reference_Feb89.pdf |archive-date=2022-02-23 |url-status=live}}</ref>

All of the data buses were at least 64 bits wide. The internal memory bus to the cache, for instance, was 128 bits wide.

The "core" class instructions use thirty-two 32-bit integer registers. But the "floating-point or graphics" instructions use a register file that can be accessed by the floating point units as either thirty-two 32-bit, sixteen 64-bit, or eight 128-bit floating-point registers, or that can be accessed by the graphics unit as sixteen 64-bit integer registers.

The "core" unit is responsible for fetching instructions, and in the normal "single-instruction" mode can fetch one 32-bit "core" or one 32-bit "floating point or graphics" instruction per cycle. But when executing in dual-instruction mode, the instruction cache is accessed as VLIW instructions consisting of a 32-bit "core" instruction paired with a 32-bit "floating-point or graphics" instruction, simultaneously fetched together over a 64-bit bus.<ref name=":1" />

Intel referred to the design as the "i860 64-Bit Microprocessor".<ref>{{cite journal
 |last1=Grimes
 |first1=Jack 
 |last2=Kohn
 |first2=L. 
 |last3=Bharadhwaj
 |first3=R.
 |title=The Intel i860 64-Bit Processor: A General-Purpose CPU with 3D Graphics Capabilities
 |pages=85–94
 |journal=IEEE Computer Graphics and Applications
 |publisher=IEEE Computer Society
 |date=July 1989
 |doi=10.1109/38.31467
 |volume=9
 |issue=4
 |s2cid=38831149 
 }}</ref>

Intel i860 instructions acted on data sizes from 8-bit through 128-bit.<ref>{{cite web
 |title=The Chip Collection - i860 Microprocessor - Smithsonian Institution
 |url=http://smithsonianchips.si.edu/intel/i860.htm
 |website=Smithsonian Institution
 }}</ref>

The graphics supports [[SIMD]]-like instructions in addition to basic 64-bit integer math. For instance, its 64-bit integer datapath can represent multiple pixels together as either 8-bit pixels, 16-bit pixels, or 32-bit pixels.<ref name=":1" /> Experience with the i860 influenced the [[MMX (instruction set)|MMX]] functionality later added to Intel's [[Pentium]] processors.

The pipelines into the functional units are program-accessible ([[VLIW]]), requiring the [[compiler]]s to order instructions carefully in the [[object code]] to keep the pipelines filled. In traditional architectures these duties were handled at runtime by a scheduler on the CPU itself, but the complexity of these systems limited their application in early RISC designs. The i860 was an attempt to avoid this entirely by moving this duty off-chip into the compiler. This allowed the i860 to devote more room to functional units, improving performance. As a result of its architecture, the i860 could run certain graphics and floating-point algorithms with exceptionally high speed, but its performance in general-purpose applications suffered and it was difficult to program efficiently (see below).

The i860 has both non-delayed and delayed branch instructions. When delayed branches are taken, the following instruction will be executed prior to transferring control to the branch target instruction. It means the i860 has a single branch delay slot.<ref>{{Cite web |url=http://www.bitsavers.org/components/intel/i860/240329-002_i860_64-Bit_Microprocessor_Programmers_Reference_Feb89.pdf#page=70 |title=i860™ 64-bit Microprocessor Programmer's Reference Manual |page=70(5-11) |accessdate=2023-12-21}}</ref>