Editing Intel 8008 (section)

==Design==
[[File:Intel 8008 arch.svg|thumb|i8008 microarchitecture]]
{| class="infobox" style="font-size:88%;width:29em;"
|+ Intel 8008 registers
|-
| style="text-align:center;"| <sup>1</sup><sub>3</sub>
| style="text-align:center;"| <sup>1</sup><sub>2</sub>
| style="text-align:center;"| <sup>1</sup><sub>1</sub>
| style="text-align:center;"| <sup>1</sup><sub>0</sub>
| style="text-align:center;"| <sup>0</sup><sub>9</sub>
| style="text-align:center;"| <sup>0</sup><sub>8</sub>
| style="text-align:center;"| <sup>0</sup><sub>7</sub>
| style="text-align:center;"| <sup>0</sup><sub>6</sub>
| style="text-align:center;"| <sup>0</sup><sub>5</sub>
| style="text-align:center;"| <sup>0</sup><sub>4</sub>
| style="text-align:center;"| <sup>0</sup><sub>3</sub>
| style="text-align:center;"| <sup>0</sup><sub>2</sub>
| style="text-align:center;"| <sup>0</sup><sub>1</sub>
| style="text-align:center;"| <sup>0</sup><sub>0</sub>
| ''(bit position)''
|-
|colspan="15" | '''Main registers'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| A
| style="width:auto; background:white; color:black;"| '''A'''ccumulator
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| B
| style="background:white; color:black;"| '''B''' register
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| C
| style="background:white; color:black;"| '''C''' register
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| D
| style="background:white; color:black;"| '''D''' register
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| E
| style="background:white; color:black;"| '''E''' register
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| H
| style="background:white; color:black;"| '''H''' register ''(indirect)''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| L
| style="background:white; color:black;"| '''L''' register ''(indirect)''
|-
|colspan="15" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|-
|colspan="15" | '''Push-down address call stack'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 2
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 3
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 4
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 5
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 6
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 7
|-
|colspan="15" | '''Flags'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="10" | &nbsp;
| style="text-align:center;"| [[Carry flag|C]]
| style="text-align:center;"| [[Parity flag|P]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| [[Sign flag|S]]
| style="background:white; color:black" | Flags<ref>{{cite book |title=8008 8 Bit Parallel Central Processor Unit |date=November 1973 |publisher=Intel |pages=14, 17 |edition=Rev 4, Second Printing |url=http://www.bitsavers.org/components/intel/MCS8/Intel_8008_8-Bit_Parallel_Central_Processing_Unit_Rev4_Nov73.pdf |access-date=30 April 2024}}</ref>{{efn|CPZS flags are presented as a group in this order during state 4 of the PCC cycle of the INP instruction.}}
|}

The 8008 was implemented in 10&nbsp;[[micrometre|μm]] silicon-gate enhancement-mode [[PMOS logic]]. Initial versions could work at clock frequencies up to 0.5&nbsp;MHz. This was later increased in the 8008-1 to a specified maximum of 0.8&nbsp;MHz. Instructions take between 3 and 11 T-states, where each T-state is 2 clock cycles.<ref name="MCS8">{{cite web |title=MCS-8 Micro Computer Set Users Manual |publisher=[[Intel Corporation]] |date=1972 |url=http://dunfield.classiccmp.org/mod8/8008um.pdf |access-date=2010-12-04}}</ref>
Register–register loads and ALU operations take 5T (20&nbsp;μs at 0.5&nbsp;MHz), register–memory 8T (32&nbsp;μs), while calls and jumps (when taken) take 11 T-states (44&nbsp;μs).<ref name="pastraiser">{{cite web |title=Intel 8008 Opcodes |url=http://www.pastraiser.com/cpu/i8008/i8008_opcodes.html |access-date=2010-12-04}}</ref>
The 8008 is a little slower in terms of [[instructions per second]] (36,000 to 80,000 at 0.8&nbsp;MHz) than the 4-bit [[Intel 4004]] and [[Intel 4040]].<ref>{{cite web |title=Intel 8008 (i8008) microprocessor family |publisher=CPU World |date=2003–2010 |url=http://www.cpu-world.com/CPUs/8008/index.html |access-date=2010-12-04}}</ref> but since the 8008 processes data 8 bits at a time and can access significantly more RAM, in most applications it has a significant speed advantage over these processors. The 8008 has 3,500 [[transistor]]s.<ref>{{cite web |url=http://www.intel.com/museum/archives/history_docs/Moore.htm |access-date=June 28, 2009 |url-status=dead |archive-url=https://web.archive.org/web/20090904175848/http://www.intel.com/museum/archives/history_docs/Moore.htm |archive-date=2009-09-04 |title=Gordon Moore and Moore's Law |author=Intel}}</ref><ref>Intel (2012). [http://www.intel.com/content/dam/www/public/us/en/documents/corporate-information/history-intel-chips-timeline-poster.pdf "Intel Chips: timeline poster"].</ref><ref>Intel (2008). [http://www.intel.com/pressroom/kits/quickreffam.htm "Microprocessor Quick Reference Guide"].</ref>

The chip, limited by its 18-pin [[dual in-line package|DIP]], has a single 8-bit bus working triple duty to transfer 8 data bits, 14 address bits, and two status bits. The small package requires about 30 TTL support chips to interface to memory.<ref>{{cite book |title=Oral History of Federico Faggin |date=22 September 2004 |publisher=Computer History Museum |page=82 |edition=X2941.2005 |url=http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf |access-date=2023-07-14}}</ref> For example, the 14-bit address, which can access "16 K × 8 bits of memory", needs to be latched by some of this logic into an external memory address register (MAR). The 8008 can access 8 [[I/O port|input ports]] and 24 output ports.<ref name="MCS8"/>

For controller and [[Computer terminal|CRT terminal]] use, this is an acceptable design, but it is rather cumbersome to use for most other tasks, at least compared to the next generations of microprocessors. A few early computer designs were based on it, but most would use the later and greatly improved [[Intel 8080]] instead.{{citation needed|date=February 2017}}

=== Related processor designs ===
The subsequent 40-pin [[NMOS logic|NMOS]] [[Intel 8080]] expanded upon the 8008 registers and instruction set and implements a more efficient external bus interface (using the 22 additional pins). Despite a close architectural relationship, the 8080 was not made binary compatible with the 8008, so an 8008 program would not run on an 8080. However, as two different assembly syntaxes were used by Intel at the time, the 8080 could be used in an 8008 assembly-language backward-compatible fashion.

The [[Intel 8085]] is an electrically modernized version of the 8080 that uses [[Depletion-load NMOS logic|depletion-mode]] transistors and also added two new instructions.

The [[Intel 8086]], the original x86 processor, is a non-strict extension of the 8080, so it loosely resembles the original Datapoint 2200 design as well. Almost every Datapoint 2200 and 8008 instruction has an equivalent not only in the instruction set of the 8080, 8085, and [[Zilog Z80|Z80]], but also in the instruction set of modern [[x86]] processors (although the instruction encodings are different).

===Features===
The 8008 architecture includes the following features:{{citation needed|date=February 2017}}
* Seven 8-bit "scratchpad" registers: The main accumulator (A) and six other registers (B, C, D, E, H, and L).
* 14-bit program counter (PC).
* Seven-level push-down address [[call stack]]. Eight registers are actually used, with the top-most register being the PC.
* Four condition code status flags: carry (C), even parity (P), zero (Z), and sign (S).
* Indirect memory access using the H and L registers (HL) as a 14-bit data pointer (the upper two bits are ignored).