Editing IA-64 (section)

=== Development ===

In 1989, HP began to become concerned that [[reduced instruction set computing]] (RISC) architectures were approaching a processing limit at one [[instruction per cycle]]. Both Intel and HP researchers had been exploring computer architecture options for future designs and separately began investigating a new concept known as [[very long instruction word]] (VLIW)<ref name="HP_Labs">{{cite web|url=http://www.hpl.hp.com/news/2001/apr-jun/itanium.html|title=Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture|date=June 2001|access-date=2007-03-23|work=[[Hewlett-Packard|HP]] Labs|archive-date=2012-03-04|archive-url=https://web.archive.org/web/20120304045612/http://www.hpl.hp.com/news/2001/apr-jun/itanium.html|url-status=dead}}</ref> which came out of research by [[Yale University]] in the early 1980s.<ref>{{cite conference | first = Joseph A. | last = Fisher | author-link = Josh Fisher | year = 1983 | title = Very Long Instruction Word architectures and the ELI-512 | conference = International Symposium on Computer Architecture | book-title = Proceedings of the 10th annual international symposium on Computer architecture | publisher = [[Association for Computing Machinery]] (ACM) | location = New York, NY, USA | pages = 140–150 | doi = 10.1145/800046.801649 | isbn = 0-89791-101-6| doi-access= free }}</ref>

VLIW is a computer architecture concept (like RISC and [[complex instruction set computing|CISC]]) where a single instruction word contains multiple instructions encoded in one very long instruction word to facilitate the processor executing multiple [[instruction (computer science)|instructions]] in each clock cycle. Typical VLIW implementations rely heavily on sophisticated compilers to determine at compile time which instructions can be executed at the same time and the proper scheduling of these instructions for execution and also to help predict the direction of branch operations. The value of this approach is to do more useful work in fewer clock cycles and to simplify processor instruction scheduling and branch prediction hardware requirements, with a penalty in increased processor complexity, cost, and energy consumption in exchange for faster execution.