Editing I486 (section)

==Improvements==
[[File:80486DX2 arch.svg|300px|thumb|The 486DX2 architecture]]
{| class="infobox" style="font-size:88%;width:34em;"
|-
|+ i486 registers
|-
|
{| style="font-size:88%"
|-
| style="width:10px; text-align:center"| <sup>3</sup><sub>1</sub>
| style="width:120px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:50px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:35px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="8" | '''Main registers''' ''(8/16/32 bits)''
|- style="background:silver;color:black;text-align:left"
| style="text-align:center" colspan="2"| EAX
| style="text-align:center" colspan="2"| AH
| style="text-align:center" colspan="3"| AL
| style="background:white; color:black"| '''A''' register
|- style="background:silver;color:black;text-align:left"
| style="text-align:center" colspan="2"| EBX
| style="text-align:center" colspan="2"| BH
| style="text-align:center" colspan="3"| BL
| style="background:white; color:black"| '''B''' register
|- style="background:silver;color:black;text-align:left"
| style="text-align:center" colspan="2"| ECX
| style="text-align:center" colspan="2"| CH
| style="text-align:center" colspan="3"| CL
| style="background:white; color:black"| '''C''' register
|- style="background:silver;color:black;text-align:left"
| style="text-align:center" colspan="2"| EDX
| style="text-align:center" colspan="2"| DH
| style="text-align:center" colspan="3"| DL
| style="background:white; color:black"| '''D''' register
|-
|colspan="8" | '''Index registers''' ''(16/32 bits)''
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| ESI
| style="text-align:center" colspan="5"| SI
| style="background:white; color:black"| '''S'''ource '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| EDI
| style="text-align:center" colspan="5"| DI
| style="background:white; color:black"| '''D'''estination '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| EBP
| style="text-align:center" colspan="5"| BP
| style="background:white; color:black"| '''B'''ase '''P'''ointer
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| ESP
| style="text-align:center" colspan="5"| SP
| style="background:white; color:black"| '''S'''tack '''P'''ointer
|-
|colspan="8" | '''Program counter''' ''(16/32 bits)''
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| EIP
| style="text-align:center" colspan="5"| IP
| style="background:white; color:black"| '''I'''nstruction '''P'''ointer
|-
|colspan="8" | '''Segment selectors''' ''(16 bits)''
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| CS
| style="background:white; color:black"| '''C'''ode '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| DS
| style="background:white; color:black"| '''D'''ata '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| ES
| style="background:white; color:black"| '''E'''xtra '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| FS
| style="background:white; color:black"| '''F''' '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| GS
| style="background:white; color:black"| '''G''' '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="5"| SS
| style="background:white; color:black"| '''S'''tack '''S'''egment
|}
|-
|
{| style="font-size:88%"
|-
|colspan="20" | '''Status register'''
|-
| style="width:20px; text-align:center"| &nbsp;
| style="width:10px; text-align:center"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF"| &nbsp;
| style="text-align:center"| [[Virtual 8086 mode|V]]
| style="text-align:center"| R
| style="text-align:center"| 0
| style="text-align:center"| N
| style="text-align:center" colspan="2"| [[IOPL]]
| style="text-align:center"| [[Overflow flag|O]]
| style="text-align:center"| [[Direction flag|D]]
| style="text-align:center"| [[IF (x86 flag)|I]]
| style="text-align:center"| [[Trap flag|T]]
| style="text-align:center"| [[Sign flag|S]]
| style="text-align:center"| [[Zero flag|Z]]
| style="text-align:center"| 0
| style="text-align:center"| [[Adjust flag|A]]
| style="text-align:center"| 0
| style="text-align:center"| [[Parity flag|P]]
| style="text-align:center"| 1
| style="text-align:center"| [[Carry flag|C]]
| style="background:white; color:black" | [[FLAGS register|EFlags]]
|}
|-
|
{| style="font-size:88%"
|-
|colspan="3" | '''Floating-point registers''' ''(80 bits)''
|-
| style="width:10px; text-align:center"| <sup>7</sup><sub>9</sub>
| style="width:245px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- style="background:silver"
| style="text-align:center" colspan="3"| ST0
| style="background:white; color:black" | '''ST'''ack register 0
|- style="background:silver"
| style="text-align:center" colspan="3"| ST1
| style="background:white; color:black" | '''ST'''ack register 1
|- style="background:silver"
| style="text-align:center" colspan="3"| ST2
| style="background:white; color:black" | '''ST'''ack register 2
|- style="background:silver"
| style="text-align:center" colspan="3"| ST3
| style="background:white; color:black" | '''ST'''ack register 3
|- style="background:silver"
| style="text-align:center" colspan="3"| ST4
| style="background:white; color:black" | '''ST'''ack register 4
|- style="background:silver"
| style="text-align:center" colspan="3"| ST5
| style="background:white; color:black" | '''ST'''ack register 5
|- style="background:silver"
| style="text-align:center" colspan="3"| ST6
| style="background:white; color:black" | '''ST'''ack register 6
|- style="background:silver"
| style="text-align:center" colspan="3"| ST7
| style="background:white; color:black" | '''ST'''ack register 7
|}
|}

The [[instruction set]] of the i486 is very similar to the i386, with the addition of a few extra instructions, such as CMPXCHG, a [[compare-and-swap]] [[atomic operation]], and XADD, a [[fetch-and-add]] atomic operation that returned the original value (unlike a standard ADD, which returns flags only).  This generation CPU has brought up to 156 different instructions listing.<ref>House, Dave, "Putting the RISC vs. CISC Debate to Rest", Intel Corporation, Microcomputer Solutions, November/December 1991, page 18</ref>

The i486's performance architecture is a vast improvement over the i386. It has an on-chip unified instruction and data [[CPU cache|cache]], an on-chip [[floating-point unit]] (FPU) and an enhanced [[computer bus|bus]] interface unit.<ref>{{FOLDOC|i486}}</ref> Due to the tight pipelining, sequences of simple instructions (such as <code>ALU reg,reg</code> and <code>ALU reg,im</code>) could sustain single-clock-cycle throughput (one instruction completed every clock). In other words, it was running about 1.8 clocks per instruction.<ref name="Chen, Allan 1989, page 12"/>  These improvements yielded a rough doubling in integer [[Arithmetic logic unit|ALU]] performance over the i386 at the same [[clock rate]]. A 16&nbsp;MHz i486 therefore had performance similar to a 33&nbsp;MHz i386. The combination of both CPU and FPU housed on a single die results in bus utilization rates of 50% for the 25 MHz Intel486 version.<ref>Intel Corporation, "Coming Attractions: Clock-Doubling Technology", Microcomputer Solutions, January/February 1992, page 6</ref> In other words, with the combination of both CPU and MCP (math coprocessor) provides 40% more performance than with both Intel386 DX and Intel387 DX math coprocessor combined.<ref>Intel Corporation, "A Guide to the Intel Architecture", Microcomputer Solutions, January/February 1992, page 11</ref>  The older design had to reach 50&nbsp;MHz to be comparable with a 25&nbsp;MHz i486 part.{{efn|The pre-DX2 i486 parts did not use a clock multiplier and are therefore comparable to a twice-higher clocked 386/286.}}

===Differences between i386 and i486===
* An 8 [[Kilobyte|KB]] on-chip (level 1) [[Static random access memory|SRAM]] [[CPU cache|cache]] stores the most recently used instructions and data (16&nbsp;KB and/or [[Cache (computing)#Operation|write-back]] on some later models). The [[i386]] had no internal cache but supported a slower off-chip cache (not officially a [[level 2 cache]] because i386 had no internal level 1 cache).
* An enhanced external bus protocol to enable cache coherency and a new burst mode for memory accesses to fill a cache line of 16 bytes within five bus cycles. The 386 needed eight bus cycles to transfer the same amount of data.
* Tightly coupled{{efn|name=fn1|The 386, 286, and even the 8086 all had overlapping fetch, decode, execution (calculation), and write back; however, '''tightly pipelined''' usually means that all stages perform their respective duties within the same length time slot. In contrast '''loosely pipelined''' implies that some kind of buffering is used to decouple the units and allow them to work more independently. Both the original 8086 and the x86-chips of today are "loosely pipelined" in this sense, while the i486 and the original Pentium worked in a "tightly pipelined" manner for typical instructions. This included most "[[Complex instruction set computing|CISC]]" type instructions as well as the simple load/store-free "[[RISC]]-like" ones, although the most complex also used some dedicated [[microcode]] control.}} [[Instruction pipeline|pipelining]] completes a simple instruction like ALU ''reg,reg'' or ALU ''reg,im'' every clock cycle (after a latency of several cycles). The i386 needed two clock cycles.
* Integrated [[floating point unit|FPU]] (disabled or absent in [[Intel 80486SX|SX models]]) with a dedicated [[local bus]]; together with faster algorithms on more extensive hardware than in the i387, this performed floating-point calculations faster than the [[i386]]/[[i387]] combination.
* Improved [[memory management unit|MMU]] performance.
* New instructions: XADD, BSWAP, CMPXCHG, INVD, WBINVD, INVLPG.

Just as in the i386, a flat 4&nbsp;GB memory model could be implemented. All "segment selector" registers could be set to a neutral value in [[protected mode]], or to zero in [[real mode]], and using only the 32-bit "offset registers" (x86-terminology for general CPU registers used as address registers) as a linear 32-bit virtual address bypassing the segmentation logic. Virtual addresses were then normally mapped onto physical addresses by the paging system except when it was disabled (''real'' mode had no ''virtual'' addresses). Just as with the i386, circumventing memory segmentation could substantially improve performance for some [[operating systems]] and applications.

On a typical PC [[motherboard]], either four matched 30-pin (8-bit) [[SIMM]]s or one 72-pin (32-bit) SIMM per bank were required to fit the i486's [[32-bit computing|32-bit]] [[bus (computing)|data bus]]. The [[address bus]] used 30-bits (A31..A2) complemented by four byte-select pins (instead of A0,A1) to allow for any 8/16/32-bit selection. This meant that the limit of directly addressable physical memory was 4&nbsp;[[gigabyte]]s as well (2<sup>30</sup> ''32-bit'' words = 2<sup>32</sup> ''8-bit'' words).