Editing Honeywell 6000 series (section)

==Hardware==
[[File:Honeywell 66 60.jpg|thumb|A Honeywell Level 66/60 mainframe computer with its cabinet door open]]

6000-series systems were said to be "memory oriented" — a ''system controller'' in each memory module arbitrated requests from other system components (processors, etc.). Memory modules contained 128&nbsp;K words of 1.2&nbsp;μs [[36-bit]] [[Word (computer architecture)|word]]s; a system could support one or two memory modules for a maximum of 256&nbsp;K words (1&nbsp;MB of 9-bit bytes). Each module provided two-way [[interleaved memory]].

Devices called ''Input/Output Multiplexers (IOMs)'' served as intelligent I/O controllers for communication with most peripherals. The IOM supported two different types of peripheral channels: ''Common Peripheral Channels'' could handle data transfer rates up to 650,000&nbsp;cps; ''Peripheral Subsystem Interface Channels'' allowed transfers up to 1.3 million cps.

The 6000 supported multiple processors and IOMs.<ref>{{cite web
|title=New Scientist |date=February 25, 1971  |page=425
|url=https://books.google.com/books?id=QqkULJdHiD4C
|quote=Honeywell makes no secret of the fact that its new 6000 series evolved from ...}}</ref> Each processor and IOM had four ports for connection to memory; each memory module had eight ports for communication with other system components, with an interrupt cell for each port.<ref name=ProductGuide>{{cite book|last=Honeywell|title=Large Systems Product Guide|date=September 1, 1980|page= Section 3.3.1, pg. 164|url=http://www.bitsavers.org/pdf/honeywell/large_systems/dps-8/Honeywell_Large_Systems_Product_Guide_198411.pdf}}</ref>

Memory protection and relocation was accomplished using a [[base and bounds]] register in the processor, the ''Base Address Register (BAR)''. The IOM was passed the contents of the BAR for each I/O request, allowing it to use virtual rather than physical addresses.

In the Multics-compatible systems there was an Appending Unit based on the unit of same name in the [[GE 645]]. This implemented the Multics model of virtual memory using "Paged Segments". These systems also had a hardware implementation of the Multics [[protection ring]] architecture, in contrast to the GE 645 which had emulated protection rings in software.<ref>{{cite journal |last1=Schroeder |first1=Michael D. |last2=Saltzer |first2=Jerome H. |title=A hardware architecture for implementing protection rings |journal=Communications of the ACM |date=March 1972 |volume=15 |issue=3 |pages=157–170 |doi=10.1145/361268.361275}}</ref> This significantly improved the performance of ring passing events in Multics compared to on the GE 645.

From the DPS-8 generation onwards GCOS could use a competing Virtual Memory architecture that was not compatible with what Multics required from the hardware. That model divided the memory space into 512 Working spaces each of which were further divided into 1024 pages (in DPS-8 implementation) of 4096KB size. On top of this GCOS implemented Segments which could be grouped together in Domains (a Domain could have segments from multiple Working Spaces) which a process could access.

A variety of communications controllers could also be used with the system.  The older [[DATANET-30]] and the DATANET 305— intended for smaller systems with up to twelve terminals attached to an IOM.<ref name=Summary>{{cite book|last=Honeywell|title=Series 6000 Summary Description|date=1971|url=http://www.bitsavers.org/pdf/honeywell/large_systems/DA48_Series_6000_Summary_Description_1971.pdf}}</ref>  The DATANET 355 processor attached directly to the system controller in a memory module and was capable of supporting up to 200 terminals.