Editing Harvard architecture (section)

===Contrast with von Neumann architectures===
{{Main|Von Neumann architecture}}
In a system with a pure [[von Neumann architecture]], instructions and data are stored in the same memory, so instructions are fetched over the same data path used to fetch data. This means that a [[Central processing unit|CPU]] cannot simultaneously read an instruction and read or write data from or to the memory. In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time,<ref name="ddj1" >"[http://www.drdobbs.com/386-vs-030-the-crowded-fast-lane/184407891?pgno=4 386 vs. 030: the Crowded Fast Lane]". ''Dr. Dobb's Journal'', January 1988.</ref> even without a [[Cache (computing)|cache]]. A Harvard architecture computer can thus be faster for a given circuit complexity because [[instruction fetch]]es and data access do not contend for a single memory pathway.

Also, a Harvard architecture machine has distinct code and data address spaces: instruction address zero is not the same as data address zero. Instruction address zero might identify a twenty-four-bit value, while data address zero might indicate an eight-bit byte that is not part of that twenty-four-bit value.