Editing Hardware description language (section)

==Structure of HDL==
HDLs are standard text-based expressions of the structure of electronic systems and their behaviour over time. Like [[concurrent programming]] languages, HDL syntax and semantics include explicit notations for expressing [[concurrency (computer science)|concurrency]]. However, in contrast to most software [[programming language]]s, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as [[netlist]] languages used in electric [[computer-aided design]]. HDL can be used to express designs in structural, behavioral or register-transfer-level architectures for the same circuit functionality; in the latter two cases the [[Logic synthesis|synthesizer]] decides the architecture and logic gate layout.

HDLs are used to write executable specifications for hardware. A program designed to implement the underlying semantics of the language statements and simulate the progress of time provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of being [[programming languages]], when they are more precisely classified as [[specification language]]s or [[modeling language]]s. Simulators capable of supporting discrete-event (digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are available.

===Comparison with control-flow languages===
It is certainly possible to represent hardware semantics using traditional programming languages such as [[C++]], which operate on [[control flow]] semantics as opposed to [[data flow]], although to function as such, programs must be augmented with extensive and unwieldy [[Class library#Object and class libraries|class libraries]]. Generally, however, software programming languages do not include any capability for explicitly expressing time, and thus cannot function as hardware description languages. Before the introduction of [[System Verilog]] in 2002, [[C++]] integration with a [[Logic simulation|logic simulator]] was one of the few ways to use [[object-oriented programming]] in hardware verification. System Verilog is the first major HDL to offer object orientation and garbage collection.

Using the proper subset of hardware description language, a program called a synthesizer, or [[Logic synthesis|logic synthesis tool]], can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives{{technical statement|date=April 2014}} to implement the specified behaviour.{{Citation needed|date=July 2010}} Synthesizers generally ignore the expression of any timing constructs in the text. Digital logic synthesizers, for example, generally use [[Clock signal|clock edges]] as the way to time the circuit, ignoring any timing constructs. The ability to have a synthesizable subset of the language does not itself make a hardware description language.