Editing GE 645 (section)

==Architecture==
=== Processor Modes ===
The GE-645 has two modes of Instruction Execution (Master and Slave) inherited from the GE-635, however it also adds another dimension by having two modes of memory addressing (Absolute and Appending). When the process is executing in Absolute Mode addressing is limited to 2<sup>18</sup> words of memory and any instructions are executed in Master mode. In comparison Append Mode calculates the address using "Appending Words" with an address space of 2<sup>24</sup> words and with instruction execution occurring in either Master or Slave modes.<ref name="AH82-00" /> 
==== Slave Mode ====
By default this is normal mode that the processor should be executing in at any point in time. Nearly all instructions will run in this mode aside from a small set of privileged instructions which cannot execute in this mode. Execution of such instructions will trigger an illegal procedure fault, also the ability to inhibit interrupts (bit 28 of instruction word) is forbidden. Format of instruction addresses is via the Appending Process.
==== Master Mode ====
In this mode the processor can execute all instructions and is able to inhibit interrupts while doing so. Like in Slave mode the default form of address formation is via the Appending Process.
==== Absolute Mode ====
All instructions can be executed in this mode and full access is given to any privileged features of the hardware. Interrupts can be inhibited and instruction fetching is limited to a 2<sup>18</sup> (18-bit) absolute address thus restricting the processor to only been able to access the lower 256 KW of physical core memory. The processor will switch to this mode in the event of a fault or interrupt and will remain in it until it executes transfer instruction whose operand address has been obtained via the appending process.

==== Appending Mode ====
By default this is normal mode of Memory addressing, both Master and Slave modes normally operate in this mode. Indirect words and operands are accessed via Appending Mechanism via the process of placing a 1 in bit 29 of the executed instruction. Effective addresses are thus either added to a base address, or the offset is linked to the base address. 
 
{| class="wikitable"
!Functions
! colspan="3" |Mode
|-
|
|Slave
|Master
|Absolute
|-
|Privileged instructions
|No
|Yes
|Yes
|-
|Interrupt inhibit (bit 28 of instruction word)
|No
|Yes
|Yes
|-
|Address for Instruction fetch
|Appending
|Appending
|Absolute
|-
|Address for Operand fetch
|Appending
|Appending
|Controlled by Bit 29 of instruction word
|-
|Restriction of access to other segments or pages
|Some
|Some (less restrictive than slave)
|N/A
|}

=== Functional Units ===
[[File:Ge645-processor.png|thumb|330x330px|GE 645 processor Functional Units]]The 645 processor was divided into four major functional units these were:<ref name="AH82-00" />

* '''Appending Unit:''' 
** Controls data I/O from memory
** Controls memory selection and interleave
** Carries out Memory appending
** Control fault recognition
** Does power on/off sequencing
* '''Associative Memory Unit:'''
** Consists of Associative Memory made up of 16 x 60-bit Registers<ref name="Schroeder">{{cite conference |last1=Schroeder |first1=Michael D. |book-title=Proceedings of the SIGOPS workshop on System performance evaluation|title=Performance of the GE-645 Associative Memory While Multics is in Operation |date=1971 |pages=227–245 |doi=10.1145/800024.808361 |url=https://dl.acm.org/doi/abs/10.1145/800024.808361 |publisher=Association for Computing Machinery|isbn=9781450373821 |s2cid=44850627 }}</ref>
** Registers point to most recently used segment (Segment Descriptor Word) or most recently used Page (Page Table)
** Performs the function of what would now be classed as a TLB.
* '''Control Unit:'''
** Performs all control functions
** Performs Address modification
** Controls the [[CPU modes|processor mode]] (master, slave, absolute)
** Interrupt recognition/handling
** Opcode decoding
* '''Operations Unit:'''
** Performs fractional and integer divisions and multiplications.
** Performs automatic alignment of floating-point numbers for addition and subtraction.
** Performs inverted divisions on floating-point numbers.
** Performs automatic normalization of floating-point resultants.
** Performs shifts.
** Performs indicator register loading and storing.
** Performs timer register loading and decrementing.

One of the key differences from the GE 635 was the addition of "appending unit" (APU) which was used to implement a hybrid "Paged Segmentation" model of [[virtual memory]]. The APU was also used to implement a [[single-level store]] which is one of the fundamental abstraction that Multics is built around. The instruction format was also extended with the previously unused bit 29 controlling whether the operand address of an instruction used an 18-bit format (bit 29 = 0) or one that was made up of a 3-bit Base Register address with a 15-bit offset (bit 29 = 1).<ref name="LSB0468">{{cite web |title=GE-645 System Manual |url=http://bitsavers.org/pdf/ge/GE-645/LSB0468_GE-645_System_Manual_Jan1968.pdf |publisher=General Electric |access-date=26 September 2023 |ref=LSB0468 |date=January 1968}}</ref>{{rp|pages=18,22}}<ref name="AH82-00">{{cite web |date=May 1972 |title=MODEL 645 PROCESSOR REFERENCE MANUAL |url=http://people.csail.mit.edu/saltzer/Multics/MHP-Saltzer-060508/bookcases/Manuals/AH82-00.ocr.pdf |access-date=26 September 2023 |publisher=Honeywell Information Systems Inc. |ref=AH82-00}}</ref>

The instruction format with bit 29 set to 1 is:
<pre>
                          1 1       2 2 2 2 3    3
        0 2 3             7 8       6 7 8 9 0    5
       +---+---------------+---------+-+-+-+------+
       |BR |       Y       |  OP     |0|I|1| Tag  |
       +---+---------------+---------+-+-+-+------+
</pre>
* '''B''' is the base register field
* '''Y''' is the address field (15 bits), addressing 32KW
* '''OP''' is the opcode (9 bits), the additional bit 27 is the ''opcode extension bit''.
* '''I''' is the interrupt inhibit bit.
* '''Tag''' indicates the type of address modification to be performed; some additional tags are supported by the GE 645.<ref name="LSB0468" />{{rp|pages=19-20}}
=== Address base registers ===
The GE 645 had 8 Address Base Registers (abr's),<ref>Organick (1972), ''op. cit., p.'' 18</ref> these could operate in either "paired" or "unpaired" modes.<ref name="Green">{{cite web |last1=Green |first1=Paul |title=Multics Virtual Memory - Tutorial and Reflections |url=https://multicians.org/pg/mvm.html |website=multicians.org |access-date=20 December 2023}}</ref> The later Honeywell 6180 changed these to 8 pointer registers. Each abr was 24-bits wide consisting of 18 bits for an address and 6 bits for control functions.<ref name=abr>Organick (1972), ''op. cit., p.'' 19</ref>

One bit of the control functions field indicates where an abr is "internal" or "external".  If an abr is internal, another 3-bit subfield of the control functions field specifies another abr with which this abr is paired; that other abr is external, with the external abr containing a segment number in the address field and the internal abr containing an offset within the segment specified by the external abr.<ref name="AH82-00" />{{rp|4{{hyp}}4}}  If an instruction or an indirect word refers to an external abr, the address field in the instruction or indirect word is used as an offset in the segment specified by the external abr.  If it refers to an internal abr, the address field in the instruction or indirect word is added to the offset in the abr, and the resulting value is used as an offset in the segment specified by the external abr with which the internal abr is paired.<ref name="AH82-00" />{{rp|6{{hyp}}26}}

The registers have the following formats depending on how bit 21 is set.<ref name="abr" />

Format as an "external" base, with bit 21 set:

<pre>
                         1 1 2 2 22 
        0                7 8 0 1 23 
       +------------------+---+-+--+
       |     PDW          |\\\|1|\\|
       +------------------+---+-+--+
</pre>

Format as a component to the effective "internal" address with a pointer to an "external" base, with bit 21 clear:

<pre>
                         1 1 2 2 22 
        0                7 8 0 1 23 
       +------------------+---+-+--+
       |     PY           |PB |0|\\|
       +------------------+---+-+--+
                                         
</pre>
* '''PDW''' is the Pointer to a descriptor word 
* '''PY''' is the component P of the effective internal address 'Y'
* '''PB''' is pointer to another base register whose bit 21 = 1


In Multics, an even-numbered abr and the following odd-numbered abr were paired. When writing in Assembly (EPLBSA/ALM)<ref group=NB>EPL BootStrap Assember / Assembly Language for Multics</ref> the standard Multics practice was to label these registers as follows:<ref>Organick (1972), ''op. cit., p.'' 20-21</ref>
* '''ap''' for abr 0
* '''ab''' for abr 1
* '''bp''' for abr 2
* '''bb''' for abr 3
* '''lp''' for abr 4
* '''lb''' for abr 5
* '''sp''' for abr 6
* '''sb''' for abr 7

The naming scheme is based around the following:<ref>Organick (1972), ''op. cit., p.'' 22-23</ref>
* '''a''' for argument-list pointer
* '''b''' for general base
* '''l''' for linkage-segment pointer
* '''s''' for stack-segment pointer

The 8 pointer registers in the Honeywell 6180 and its successors served the same purpose as the 4 paired base registers in the GE-645, referring to an offset within a segment.