Editing CDC 6600 (section)

==Description==
Typical machines of the 1950s and 1960s used a single [[central processing unit]] (CPU) to drive the entire system.<ref>{{cite journal
|journal = Communications of the ACM
|volume = 53
|number = 12
|date = December 2010
|doi = 10.1145/1859204.1859216
|pages = 28–30
|publisher = [[Association for Computing Machinery]] 
|url=https://cacm.acm.org/magazines/2010/12/102128-ibms-single-processor-supercomputer-efforts
|first1=Mark |last1=Smotherman |first2=Dag |last2=Spicer
|title=IBM's Single-Processor Supercomputer Efforts|s2cid = 23816526
}}</ref> A typical program would first load data into memory (often using pre-rolled library code), process it, and then write it back out. This required the CPUs to be fairly complex in order to handle the complete set of instructions they would be called on to perform. A complex CPU implied a large CPU, introducing signalling delays while information flowed between the individual modules making it up. These delays set a maximum upper limit on performance, as the machine could only operate at a cycle speed that allowed the signals time to arrive at the next module.

Cray took another approach. In the 1960s, CPUs generally ran slower than the [[Computer data storage#Primary storage|main memory]] to which they were attached. For instance, a processor might take 15 cycles to multiply two numbers, while each memory access took only one or two cycles. This meant there was a significant time where the main memory was idle. It was this idle time that the 6600 exploited.

The CDC 6600 used a simplified central processor (CP) that was designed to run mathematical and logic operations as rapidly as possible, which demanded it be built as small as possible to reduce the length of wiring and the associated signalling delays. This led to the machine's (typically) cross-shaped main chassis with the circuit boards for the CPU arranged close to the center, and resulted in a much smaller CPU. Combined with the faster switching speeds of the silicon transistors, the new CPU ran at 10&nbsp;MHz (100&nbsp;ns cycle time), about ten times faster than other machines on the market. In addition to the clock being faster, the simple processor executed instructions in fewer clock cycles; for instance, the CPU could complete a multiplication in ten cycles.

Supporting the CPU were ten 12-bit 4 KiB peripheral processors (PPs), each with access to a common pool of 12 [[Channel I/O|input/output (I/O) channels]], that handled input and output, as well as controlling what data were sent into central memory for processing by the CP. The PPs were designed to access memory during the times when the CPU was busy performing operations. This allowed them to perform [[input/output]] essentially for free in terms of central processing time, keeping the CPU busy as much as possible.

The 6600's CP used a 60-bit word and a [[ones' complement]] representation of integers, something that later CDC machines would use into the late 1980s, making them the last systems besides some [[digital signal processor]]s to use this architecture.<ref>The [[UNIVAC 1100/2200 series]] still provides a ones'-complement environment, but using two's complement hardware.</ref>

Later,{{When|date=May 2022}} CDC offered options as to the number and type of CPs, PPs and channels, e.g., the [[CDC 6700]] had two central processors, a [[CDC 6400|6400]] CP and a 6600 CP.

While other machines of its day had elaborate [[front panel]]s to control them, the 6600 has only a ''dead start panel''.<ref>{{cite book
 | title       = Control Data - 6000 Series - Computer Systems
 | section     = Figure 6-1. Dead Start Panel
 | section-url = http://bitsavers.org/pdf/cdc/cyber/cyber_70/60100000AL_6000_Series_Computer_Systems_HW_Reference_Aug78.pdf#page=125
 | page        = 6-3 
 | url         = http://bitsavers.org/pdf/cdc/cyber/cyber_70/60100000AL_6000_Series_Computer_Systems_HW_Reference_Aug78.pdf
 | access-date = October 6, 2023
 }}
</ref> There is a dual CRT system console, but it is controlled by the operating system and neither controls nor displays the hardware directly.

The entire 6600 machine contained approximately 400,000 transistors.<ref>{{cite book 
|last=Thornton
|first=James
|author-link=James E. Thornton
|date=December 1, 1970
|title=Design of a Computer: the Control Data 6600
|isbn=978-0673059536
|page=20
|url=https://archive.org/details/CDC6600Thornton
}}</ref>