Editing AltiVec (section)

==Development history==
The Power Vector Media Extension (VMX) was developed between 1996 and 1998 by a collaborative project between Apple, IBM, and Motorola. 
Apple was the primary customer for Power Vector Media Extension (VMX) until Apple switched to Intel-made, x86-based CPUs on June 6, 2005. They used it to accelerate [[multimedia]] applications such as [[QuickTime]], [[iTunes]] and key parts of Apple's [[Mac OS X]] including in the [[Quartz (graphics layer)|Quartz graphics compositor]].  Other companies such as Adobe used AltiVec to optimize their image-processing programs such as [[Adobe Photoshop]]. Motorola was the first to supply AltiVec enabled processors starting with their G4 line.  AltiVec was also used in some embedded systems for high-performance digital signal processing.

IBM consistently left VMX out of their earlier [[IBM Power microprocessors|POWER microprocessors]], which were intended for server applications where it was not very useful. The [[POWER6]] microprocessor, introduced in 2007, implements AltiVec. The last desktop microprocessor from IBM, the [[PowerPC 970]] (dubbed the "G5" by Apple) also implemented AltiVec with hardware similar to that of the [[PowerPC G4|PowerPC 7400]].

AltiVec is a brandname trademarked by Freescale (previously Motorola) for the standard ''Category:Vector'' part of the [[Power ISA#Power ISA v.2.03|Power ISA v.2.03]]<ref name="isa203" /> specification.  This category is also known as VMX (used by IBM), and "Velocity Engine" (a brand name previously used by Apple).

The [[Cell microprocessor|Cell]] Broadband Engine, used in (amongst other things) the [[PlayStation 3]], also supports Power Vector Media Extension (VMX) in its PPU, with the SPU ISA being enhanced but architecturally similar.

Freescale is bringing an enhanced version of AltiVec to [[PowerPC e6500|e6500]] based [[QorIQ]] processors.

=== VMX128 ===
IBM enhanced VMX for use in [[Xenon (processor)|Xenon]] (Xbox 360) and called this enhancement VMX128. The enhancements comprise new routines targeted at gaming (accelerating 3D graphics and game physics)<ref>{{cite web
 |title=The Microsoft Xbox 360 CPU story 
 |publisher=IBM
 |url=http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw09XBoxDesign 
 |url-status=bot: unknown 
 |archive-url=https://web.archive.org/web/20080120000613/http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw09XBoxDesign 
 |archive-date=2008-01-20 
|date=October 2015
 }}</ref> and a total of 128 registers. VMX128 is not entirely compatible with VMX/Altivec, as a number of integer operations were removed to make space for the larger register file and additional application-specific operations.<ref>[https://web.archive.org/web/20120208052530/http://domino.research.ibm.com/comm/research.nsf/pages/r.arch.simd.html Using data-parallel SIMD architecture in video games and supercomputers] IBM Research</ref><ref>[https://patents.google.com/patent/US7421566  Implementing instruction set architectures with non-contiguous register file specifiers]  US Patent 7,421,566</ref>

=== VSX (Vector Scalar Extension) ===
[[Power ISA#Power ISA v.2.06|Power ISA v2.06]] introduced VSX vector-scalar instructions<ref name="vsx">{{cite web
	|title=Workload acceleration with the IBM POWER vector-scalar architecture
	|publisher=IBM
	|date=2016-03-01
	|url=https://www.researchgate.net/publication/299472451
	|access-date=2017-05-02
	|archive-date=2022-01-25
	|archive-url=https://web.archive.org/web/20220125060920/https://www.researchgate.net/publication/299472451_Workload_acceleration_with_the_IBM_POWER_vector-scalar_architecture
	|url-status=live
	}}</ref> which extend SIMD processing for the Power ISA to support up to 64 registers, with support for regular floating point, decimal floating point and vector execution. [[POWER7]] is the first Power ISA processor to implement Power ISA v2.06.

New instructions are introduced by IBM under the Vector Media Extension category for integer operations as part of the VSX extension in Power ISA 2.07.

New integer vector instructions were introduced by IBM following the VMX encodings as part of the VSX extension in  Power ISA v3.0. Shall be introduced with [[POWER9]] processors.<ref>{{Cite web | url=https://sourceware.org/ml/binutils/2015-11/msg00071.html | title=Peter Bergner - &#91;PATCH, COMMITTED&#93; Add full Power ISA 3.0 / POWER9 binutils support | access-date=2016-12-24 | archive-date=2016-03-07 | archive-url=https://web.archive.org/web/20160307013258/https://sourceware.org/ml/binutils/2015-11/msg00071.html | url-status=live }}</ref>