Editing Zilog Z80 (section)

=== Compatible peripherals ===
Zilog introduced a number of peripheral parts for the Z80, which all support the Z80's interrupt handling system and I/O address space. These include the counter/timer channel (CTC),<ref>{{Cite web |last=<!--Staff writer(s); no by-line.--> |date=2001 |title=Z80 Family CPU Peripherals User Manual |url=http://datasheet.eeworld.com.cn/pdf/ZILOG/68012_Z80.pdf |url-status=dead |archive-url=https://web.archive.org/web/20140502033449/http://datasheet.eeworld.com.cn/pdf/ZILOG/68012_Z80.pdf |archive-date=May 2, 2014 |access-date=April 30, 2014 |website=EEWORLD Datasheet |publisher=ZiLOG}}</ref> the SIO (serial input/output), the DMA (direct memory access), the PIO (parallel input/output) and the DART (dual asynchronous receiver–transmitter). As the product line developed, low-power, high-speed and [[CMOS]] versions of these chips were introduced.

<gallery mode="packed">
File:Basic Measuring Instruments - Math Processor 83002190 - Zilog Z80 PIO Z84C2008PEC-3919.jpg|PIO Z84C2008
File:Basic Measuring Instruments - Math Processor 83002190 - Zilog Z80 CTC Z84C3008PEC-3918.jpg|CTC Z84C3008
File:Basic Measuring Instruments - Math Processor 83002190 - Zilog Z80 SIO Z84C4008PEC-3920.jpg|SIO Z84C4008
</gallery>

Like the 8080, 8085 and 8086 processors, but unlike processors such as the Motorola 6800 and MOS Technology 6502, the Z80 and 8080 has a separate control line and address space for I/O instructions. While some Z80-based computers such as the [[Osborne 1]] used "Motorola-style" [[Memory-mapped I/O|memory mapped input/output]] devices, usually the I/O space was used to address one of the Zilog peripheral chips compatible with the Z80. During the timing for an I/O read or an I/O write operation, a single wait cycle is automatically inserted by the Z80.<ref>{{Cite web |title=Sharp 1986 Semiconductor Data Book |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=225 |access-date=January 1, 2024 |page=218 |archive-date=January 1, 2024 |archive-url=https://web.archive.org/web/20240101005825/http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=225 |url-status=live }}</ref> Zilog I/O chips supported the Z80's new mode 2 interrupts which simplified interrupt handling for large numbers of peripherals.

The Z80 was officially described as supporting 16-bit (64&nbsp;KB) memory addressing, and 8-bit (256 ports) I/O-addressing. All I/O instructions actually assert the entire 16-bit address bus. OUT&nbsp;(C),reg and IN&nbsp;reg,(C) places the contents of the entire 16-bit BC register on the address bus;<ref name="Young 1998">{{Cite web |last=Young |first=Sean |date=October 1998 |title=Z80 Undocumented Features (in software behaviour) |url=http://z80.info/z80undoc3.txt |url-status=live |archive-url=https://web.archive.org/web/20231225235537/http://z80.info/z80undoc3.txt |archive-date=December 25, 2023 |quote=The I/O instructions use the whole of the address bus, not just the lower 8 bits. So in fact, you can have 65536 I/O ports in a Z80 system (the Spectrum uses this). IN r,(C), OUT (C),r and all the I/O block instructions put the whole of BC on the address bus. IN A,(n) and OUT (n),A put A*256+n on the address bus.}}</ref> OUT&nbsp;(n),A and IN&nbsp;A,(n) places the contents of the A&nbsp;register on b8–b15 of the address bus and n on b0–b7 of the address bus. A designer could choose to decode the entire 16-bit address bus on I/O operations in order to take advantage of this feature, or use the high half of the address bus to select subfeatures of the I/O device. This feature has also been used to minimise decoding hardware requirements, such as in the [[Amstrad CPC]]/[[Amstrad PCW|PCW]] and [[ZX81]].