Editing Transputer (section)

== Adoption ==
[[File:Transputer.jpg|thumb|Transputer-based computer (left)]]
While the transputer was simple but powerful compared to many contemporary designs, it never came close to meeting its goal of being used universally in both CPU and microcontroller roles. In the microcontroller market, the market was dominated by 8-bit machines where cost was the most serious consideration. Here, even the T2s were too powerful and costly for most users.

In the [[computer desktop]] and [[workstation]] field, the transputer was fairly fast (operating at about 10 million [[instructions per second]] (MIPS) at 20&nbsp;MHz). This was excellent performance for the early 1980s, but by the time the [[floating-point unit]] (FPU) equipped T800 was shipping, other RISC designs had surpassed it. This could have been mitigated to a large extent if machines had used multiple transputers as planned, but T800s cost about $400 each when introduced, which meant a poor price/performance ratio. Few transputer-based workstation systems were designed; the most notable likely being the [[Atari Transputer Workstation]].

The transputer was more successful in the field of [[massively parallel]] computing, where several vendors produced transputer-based systems in the late 1980s. These included [[Meiko Scientific]] (founded by ex-Inmos employees), [[Floating Point Systems]], [[Parsytec]],<ref>{{cite conference|url=https://books.google.com/books?id=Hfnj5WmFVNUC&pg=PA1047|title=Virtual Channels for Deadlock-Free Communication in Transputer Networks|author=Harald W. Wabnig|conference=1993 World Transputer Congress|date=20–22 September 1993|location=Aachen, Germany|page=1047|isbn=9789051991406}}</ref> and Parsys. Several British academic institutions founded research activities in the application of transputer-based parallel systems, including [[Bristol Polytechnic]]'s Bristol Transputer Centre and the [[University of Edinburgh]]'s [[Edinburgh Concurrent Supercomputer]] Project. Also, the Data Acquisition and Second Level Trigger systems of the High Energy Physics [[ZEUS (particle detector)|ZEUS]] Experiment for the [[Hadron Elektron Ring Anlage]] (HERA) collider at [[DESY]] was based on a network of over 300 synchronously clocked transputers divided into several subsystems. These controlled both the readout of the custom detector electronics and ran reconstruction algorithms for physics event selection.

The parallel processing abilities of the transputer were put to use commercially for [[image processing]] by the world's largest printing company, [[RR Donnelley & Sons]], in the early 1990s. The ability to quickly transform digital images in preparation for print gave the firm a significant edge over their competitors. This development was led by Michael Bengtson in the RR Donnelley Technology Center. Within a few years, the processing ability of even desktop computers ended the need for custom multi-processing systems for the firm.{{Citation needed|date=March 2009}}

The German company Jäger Messtechnik used transputers for their early ADwin real-time [[data acquisition]] and control products.<ref>{{cite web |url=http://talontechsales.com/ADwinbrochure.pdf |title=ADwin Fast Real-Time Automation System |access-date=2011-11-16 |url-status=dead |archive-url=https://web.archive.org/web/20120425230828/http://talontechsales.com/ADwinbrochure.pdf |archive-date=2012-04-25 }}</ref>

A French company built the Archipel Volvox Supercomputer with up to 144 T800 and T400 Transputers. It was controlled by a Silicon Graphics Indigo2 running UNIX and a special card that interfaced to the Volvox backplanes.

Transputers also found use in protocol analysers such as the Siemens/Tektronix K1103 and in military applications where the array architecture suited applications such as radar and the serial links (that were high speed in the 1980s) served well to save cost and weight in sub-system communications.

The transputer also appeared in products related to [[virtual reality]] such as the ProVision 100 system made by Division Limited of Bristol, featuring a combination of [[Intel i860]], [[Intel 80486|80486]]/33 and [[Toshiba]] HSP processors, together with T805 or T425 transputers, implementing a [[Rendering (computer graphics)|rendering engine]] that could then be accessed as a [[server (computing)|server]] by [[IBM PC|PC]], [[Sun SPARCstation]] or [[VAX]] systems.<ref name="ProVision PCW">{{cite news |last=Edmunds |first=Nick |title=When two worlds collide |work=Personal Computer World |date=July 1993}}</ref><ref name="Bangay 1993">{{cite book |last=Bangay |first=Sean |title=Parallel Implementation of a Virtual Reality System on a Transputer Architecture. |url=http://www.cs.ru.ac.za/research/groups/vrsig/pastprojects/001parallelanddistributedvr/paper01.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.cs.ru.ac.za/research/groups/vrsig/pastprojects/001parallelanddistributedvr/paper01.pdf |archive-date=2022-10-09 |url-status=live |access-date=2012-05-06 |date=July 1993 |publisher=Rhodes University}}</ref>

[[Myriade]], a European [[miniaturized satellite]] platform developed by [[Astrium Satellites]] and [[CNES]] and used by satellites such as the [[Picard (satellite)|Picard]], is based on the T805 yielding around 4 MIPS and is scheduled to stay in production until about 2015.<ref>
{{cite web
|title= The Myriade Platform
|url= http://smsc.cnes.fr/MYRIADE/GP_plateforme.htm
|access-date= 2011-08-22
}}</ref><ref>
{{cite web
 |title       = The Design of Space Systems
 |author      = David Chemouil
 |url         = http://www.ensta-bretagne.fr/mda/ecoleMDA2006/Abstract/chemouil%20MDE4DRES.pdf
 |access-date = 2011-08-22
 |url-status    = dead
 |archive-url = https://web.archive.org/web/20120321031218/http://www.ensta-bretagne.fr/mda/ecoleMDA2006/Abstract/chemouil%20MDE4DRES.pdf
 |archive-date= 2012-03-21
}}</ref>

The asynchronous operation of the communications and computation allowed the development of asynchronous algorithms, such as Bane's "Asychronous Polynomial Zero Finding" algorithm.<ref>T.L. Freeman and M.K. Bane, "''Asynchronous Polynomial Zero-Finding Algorithms''". Parallel Computing 17, pp. 673-681. (1991)</ref> The field of asynchronous algorithms, and the asynchronous implementation of current algorithms, is likely to play a key role in the move to [[exascale computing]].

The [[High Energy Transient Explorer]] 2 (HETE-2) spacecraft used 4× T805 transputers and 8× DSP56001 yielding about 100 million [[instructions per second]] (MIPS) of performance.<ref name=HETE-sc>[http://space.mit.edu/HETE/spacecraft.html HETE-2 Spacecraft]</ref>