Editing System on a chip (section)

=== Targets ===
==== Power consumption ====
SoCs are optimized to minimize the [[Electric power#Definition|electrical power]] used to perform the SoC's functions. Most SoCs must use low power. SoC systems often require long [[battery life]] (such as [[smartphone]]s), can potentially spend months or years without a power source while needing to maintain autonomous function, and often are limited in power use by a high number of [[Embedded system|embedded]] SoCs being [[Distributed computing|networked together]] in an area. Additionally, energy costs can be high and conserving energy will reduce the [[total cost of ownership]] of the SoC. Finally, [[waste heat]] from high energy consumption can damage other circuit components if too much heat is dissipated, giving another pragmatic reason to conserve energy. The amount of energy used in a circuit is the [[integral]] of [[Power (physics)|power]] consumed with respect to time, and the [[Mean value theorem|average rate]] of power consumption is the product of [[Electric current|current]] by [[voltage]]. Equivalently, by [[Ohm's law]], power is current squared times resistance or voltage squared divided by [[Resistance (physics)|resistance]]:

<math display="block">P = IV = \frac{V^2}{R} = {I^2}{R}</math>SoCs are frequently embedded in [[Mobile device|portable devices]] such as [[smartphones]], [[GPS navigation device]]s, digital [[Digital watch|watches]] (including [[smartwatch]]es) and [[netbook]]s. Customers want long battery lives for [[mobile computing]] devices, another reason that power consumption must be minimized in SoCs. [[Multimedia application]]s are often executed on these devices, including video games, [[video streaming]], [[image processing]]; all of which have grown in [[computational complexity]] in recent years with user demands and expectations for higher-[[Video quality|quality]] multimedia. Computation is more demanding as expectations move towards [[3D video]] at [[high resolution]] with [[List of video compression formats|multiple standards]], so SoCs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery.<ref name=":1" />{{Rp|3}}

==== Performance per watt ====
{{See also|Green computing}}
SoCs are optimized to maximize [[power efficiency]] in performance per watt: maximize the performance of the SoC given a budget of power usage. Many applications such as [[edge computing]], [[distributed processing]] and [[ambient intelligence]] require a certain level of [[Computer performance|computational performance]], but power is limited in most SoC environments. 

==== Waste heat ====
{{Main|Heat generation in integrated circuits}}{{See also|Thermal management (electronics)|Thermal design power|label 1=Thermal management in electronics}}
SoC designs are optimized to minimize [[waste heat]] [[dissipation|output]] on the chip. As with other [[integrated circuit]]s, heat generated due to high [[power density]] are the [[Bottleneck (engineering)|bottleneck]] to further [[miniaturization]] of components.<ref name=":2">{{Cite book|title=Heat Management in Integrated circuits: On-chip and system-level monitoring and cooling|last=Ogrenci-Memik|first=Seda|publisher=The Institution of Engineering and Technology|year=2015|isbn=978-1-84919-935-3|location=London, United Kingdom|oclc=934678500}}</ref>{{Rp|1}} The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erode [[Reliability (semiconductor)|reliability]] of the circuit over time. High temperatures and thermal stress negatively impact reliability, [[stress migration]], decreased [[mean time between failures]], [[electromigration]], [[wire bonding]], [[Metastability (electronics)|metastability]] and other performance degradation of the SoC over time.<ref name=":2" />{{Rp|2–9}}

In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system. Because of high [[transistor count]]s on modern devices, oftentimes a layout of sufficient throughput and high [[Transistors density|transistor density]] is physically realizable from [[Semiconductor device fabrication|fabrication processes]] but would result in unacceptably high amounts of heat in the circuit's volume.<ref name=":2" />{{Rp|1}}

These thermal effects force SoC and other chip designers to apply conservative [[design margin]]s, creating less performant devices to mitigate the risk of [[catastrophic failure]]. Due to increased [[Transistors density|transistor densities]] as length scales get smaller, each [[Semiconductor node|process generation]] produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous [[heat flux]]es, which cannot be effectively mitigated by uniform [[passive cooling]].<ref name=":2" />{{Rp|1}}

==== Throughput ====
{{Expand section|date=October 2018}}
SoCs are optimized to maximize computational and communications [[throughput]].

==== Latency ====
{{Expand section|date=October 2018}}
SoCs are optimized to minimize [[Latency (engineering)|latency]] for some or all of their functions. This can be accomplished by [[Integrated circuit layout|laying out]] elements with proper proximity and [[Locality of reference|locality]] to each-other to minimize the interconnection delays and maximize the speed at which data is communicated between modules, [[Execution unit|functional units]] and memories. In general, optimizing to minimize latency is an [[NP-completeness|NP-complete]] problem equivalent to the [[Boolean satisfiability problem]].

For [[Task (computing)|tasks]] running on processor cores, latency and throughput can be improved with [[Scheduling (computing)|task scheduling]]. Some tasks run in application-specific hardware units, however, and even task scheduling may not be sufficient to optimize all software-based tasks to meet timing and throughput constraints.