Editing Phase-locked loop (section)

===Phase detector===
{{Main|phase detector}}
A phase detector (PD) generates a voltage, which represents the phase difference between two signals. In a PLL, the two inputs of the phase detector are the reference input and the feedback from the VCO. The PD output voltage is used to control the VCO such that the phase difference between the two inputs is held constant, making it a negative feedback system.
<ref>{{Cite book|last1=Basab Bijoy Purkayastha|title=A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel|last2=Kandarpa Kumar Sarma|publisher=Springer (India) Pvt. Ltd. (Part of Springer Scinece+Business Media)|year=2015|isbn=978-81-322-2040-4|location=India|pages=94}}</ref>

Different types of phase detectors have different performance characteristics.

For instance, the [[frequency mixer]] produces harmonics that adds complexity in applications where spectral purity of the VCO signal is important. The resulting unwanted (spurious) sidebands, also called "[[reference spurs]]" can dominate the filter requirements and reduce the capture range well below or increase the lock time beyond the requirements. In these applications the more complex digital phase detectors are used which do not have as severe a reference spur component on their output. Also, when in lock, the steady-state phase difference at the inputs using this type of phase detector is near 90 degrees.{{citation needed|date=August 2018}}

In PLL applications it is frequently required to know when the loop is out of lock. The more complex digital phase-frequency detectors usually have an output that allows a reliable indication of an out of lock condition.

An [[XOR gate]] is often used for digital PLLs as an effective yet simple phase detector. It can also be used in an analog sense with only slight modification to the circuitry.