Editing Motorola 68000 (section)

==Instruction set details==
The standard [[addressing mode]]s are:

*Register direct
**data register, e.g. "D0"
**address register, e.g. "A0"
*Register indirect
**Simple address, e.g. (A0)
**Address with post-increment, e.g. (A0)+
**Address with pre-decrement, e.g. −(A0)
**Address with a 16-bit signed offset, e.g. 16(A0)
**Register indirect with index register & 8-bit signed offset e.g. 8(A0,D0) or 8(A0,A1)
*:Note that for (A0)+ and −(A0), the actual increment or decrement value is dependent on the operand size: a byte access adjusts the address register by 1, a word by 2, and a long by 4.
*PC (program counter) relative with displacement
**Relative 16-bit signed offset, e.g. 16(PC). This mode was very useful for position-independent code.
**Relative with 8-bit signed offset with index, e.g. 8(PC,D2)
*Absolute memory location
**Either a number, e.g. "$4000", or a symbolic name translated by the assembler
**Most 68000 assemblers used the "$" symbol for [[hexadecimal]], instead of "0x" or a trailing H.
**There are 16 and 32-bit versions of this addressing mode
*Immediate mode
**Data stored in the instruction, e.g. "#400"
*Quick immediate mode
**3-bit unsigned (or 8-bit signed with moveq) with value stored in opcode
**In addq and subq, 0 is the equivalent to 8
**e.g. moveq #0,d0 was quicker than clr.l d0 (though both made D0 equal to 0)

Plus: access to the [[status register]], and, in later models, other special registers.

Most instructions have variants that operate on 8-bit bytes, 16-bit words, and 32-bit longs; assembler languages use dot-letter suffixes ".b", ".w", and ".l" after the instruction mnemonic to indicate the variant.

Like many CPUs of its era the cycle timing of some instructions varied depending on the source operand(s). For example, the unsigned multiply instruction takes (38+2n) clock cycles to complete where 'n' is equal to the number of bits set in the operand.<ref>{{cite web|url=http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/timstandard.HTML|title=Standard Instruction Execution Times|website=oldwww.nvg.ntnu.no|access-date=August 4, 2017|archive-date=September 9, 2016|archive-url=https://web.archive.org/web/20160909080206/http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/timstandard.HTML|url-status=live}}</ref> To create a function that took a fixed cycle count required the addition of extra code after the multiply instruction. This would typically consume extra cycles for each bit that wasn't set in the original multiplication operand.

Most instructions are '''[[wikt:dyadic|dyadic]]''', that is, the operation has a source, and a destination, and the destination is changed. Notable instructions are:

*Arithmetic: ADD, SUB, MULU (unsigned multiply), MULS (signed multiply), DIVU (unsigned divide), DIVS (signed divide), NEG (additive negation), and CMP (comparison, done by subtracting the arguments and setting the status bits without storing the result)
*[[Binary-coded decimal]] arithmetic: ABCD, NBCD, and SBCD
*Logic: EOR (exclusive or), AND, NOT (logical not), OR (inclusive or)
*Shifting: (logical, i.e. right shifts put zero in the most-significant bit) LSL, LSR, ([[arithmetic shift]]s, i.e. sign-extend the most-significant bit) ASR, ASL, (rotates through eXtend and not) ROXL, ROXR, ROL, ROR
*[[Bit test and manipulation]] in memory or data register: BSET (set to 1), BCLR (clear to 0), BCHG (invert) and BTST (no change). All of these instructions first test the destination bit and set (clear) the CCR Z bit if the destination bit is 0 (1), respectively.
*[[Multiprocessing]] control: TAS, [[test-and-set]], performed an indivisible bus operation, permitting [[semaphore (programming)|semaphore]]s to be used to synchronize several processors sharing a single memory
*Flow of control: JMP (jump), JSR (jump to subroutine), BSR (relative address jump to subroutine), RTS (return from [[subroutine]]), RTE (return from [[Interrupt|exception]], i.e. an interrupt), TRAP (trigger a software exception similar to software interrupt), CHK (a conditional software exception)
*Branch: Bcc (where the "cc" specified one of 14 tests of the condition codes in the status register: equal, greater than, less-than, carry, and most combinations and logical inversions, available from the status register). The remaining two possible conditions (always true and always false) have separate instruction mnemonics, BRA (branch always), and BSR (branch to subroutine). 
*Decrement-and-branch: DBcc (where "cc" was as for the branch instructions), which, provided the condition was '''false''', decremented the low word of a D-register and, if the result was not -1 ($FFFF), branched to a destination. This use of −1 instead of 0 as the terminating value allowed the easy coding of loops that had to do nothing if the count was 0 to start with, with no need for another check before entering the loop. This also facilitated nesting of DBcc.