Editing Accelerated Graphics Port (section)

==Connector pinout==
The AGP connector contains almost all PCI signals, plus several additions. The connector has 66 contacts on each side, although 4 are removed for each keying notch. Pin&nbsp;1 is closest to the I/O bracket, and the B and A sides are as in the table, looking down at the motherboard connector.

Contacts are spaced at 1&nbsp;mm intervals, however they are arranged in two staggered vertical rows so that there is 2&nbsp;mm space between pins in each row. Odd-numbered A-side contacts, and even-numbered B-side contacts are in the lower row (1.0 to 3.5&nbsp;mm from the card edge). The others are in the upper row (3.7 to 6.0&nbsp;mm from the card edge).

{|class=wikitable style="text-align:center"
|+ Accelerated Graphics Port connector pinout<ref name=agp10>{{Citation |url=http://www.playtool.com/pages/agpcompat/agp10.pdf |archive-url=https://web.archive.org/web/20150503042109/http://www.playtool.com/pages/agpcompat/agp10.pdf |url-status=dead |archive-date=May 3, 2015 |title=Accelerated Graphics Port Interface Specification Revision 1.0 |author=Intel |date=July 31, 1996 |access-date=2007-10-18 }}</ref>{{rp|95}}<ref name=agp20>{{Citation |url=http://www.motherboards.org/files/techspecs/agp20.pdf |title=Accelerated Graphics Port Interface Specification Revision 2.0 |author=Intel |date=May 4, 1998 |access-date=2014-09-15 |archive-url=https://web.archive.org/web/20141231081259/http://www.motherboards.org/files/techspecs/agp20.pdf |archive-date=December 31, 2014 |url-status=dead }}</ref>{{rp|231–3}}<ref name=agp30>{{Citation |url=http://download.intel.com/support/motherboards/desktop/sb/agp30.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://download.intel.com/support/motherboards/desktop/sb/agp30.pdf |archive-date=2022-10-09 |url-status=live |title=AGP V3.0 Interface Specification |author=Intel |date=September 2002 |access-date=2011-10-09}}</ref>{{rp|50}}
|-
! Pin !! Side B !!colspan=2| Side A !! Comments
|-
!  1
|style="background:#f69"| OVERCNT# ||style="background:silver" colspan=2| +12&nbsp;V ||align=left| USB port overcurrent warning
|-
!  2
|style="background:silver"| +5&nbsp;V ||style="background:#f69" colspan=2| TYPEDET# ||align=left| Pulled low by card to indicate 1.5&nbsp;V (AGP 2.0 4x) ability
|-
!  3
|style="background:silver"| +5&nbsp;V ||style="background:#f69" colspan=2| GC_DET# ||align=left| Pulled low by card to indicate 0.8&nbsp;V (AGP 3.0 8x) ability
|-
!  4
|style="background:#9f9"| USB+ ||style="background:#9f9" colspan=2| USB− ||align=left| USB pins for pass through to monitor
|-
!  5
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground ||align=left|
|-
!  6
|style="background:#fc6"| INTB# ||style="background:#fc6" colspan=2| INTA# ||align=left| Interrupt lines (open-drain)
|-
!  7
|style="background:#66f"| CLK ||style="background:#66f" colspan=2| RST# ||align=left| 66&nbsp;MHz clock, Bus reset
|-
!  8
|style="background:#f69"| REQ# ||style="background:#66f" colspan=2| GNT# ||align=left| Bus request from card, and grant from motherboard
|-
!  9
|style="background:silver"| +3.3&nbsp;V ||style="background:silver" colspan=2| +3.3&nbsp;V ||align=left|
|-
! 10
|style="background:#66f"| ST[0] ||style="background:#66f" colspan=2| ST[1] ||align=left| AGP status (valid while GNT# low)
|-
! 11
|style="background:#66f"| ST[2] ||style="background:#66f" colspan=2| MB_DET# ||align=left| Pulled low by motherboard to indicate 0.8&nbsp;V (AGP 3.0 8x) ability
|-
! 12
|style="background:#f69"| RBF# ||style="background:#f69"| PIPE# ||style="background:#9f9"| DBI_HI ||align=left| Read buffer full, Pipeline request, Data bus inversion[31:16]
|-
! 13
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground ||align=left|
|-
! 14
|style="background:#9f9"| DBI_LO ||style="background:#f69" colspan=2| WBF# ||align=left| Data bus inversion [15:0], Write buffer full
|-
! 15
|style="background:#f69"| SBA[0] ||style="background:#f69" colspan=2| SBA[1] ||rowspan=7 align=left| Sideband address bus
|-
! 16
|style="background:silver"| +3.3&nbsp;V ||style="background:silver" colspan=2| +3.3&nbsp;V
|-
! 17
|style="background:#f69"| SBA[2] ||style="background:#f69" colspan=2| SBA[3]
|-
! 18
|style="background:#f69"| SB_STB ||style="background:#f69" colspan=2| SB_STB#
|-
! 19
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground
|-
! 20
|style="background:#f69"| SBA[4] ||style="background:#f69" colspan=2| SBA[5]
|-
! 21
|style="background:#f69"| SBA[6] ||style="background:#f69" colspan=2| SBA[7]
|-
! 22
|style="background:#ff9"| Reserved ||style="background:#ff9" colspan=2| Reserved ||rowspan=4 align=left| Key notch for 3.3&nbsp;V AGP cards
|-
! 23
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground
|-
! 24
|style="background:silver"| +3.3&nbsp;V aux ||style="background:#ff9" colspan=2| Reserved
|-
! 25
|style="background:silver"| +3.3&nbsp;V ||style="background:silver" colspan=2| +3.3&nbsp;V
|-
! 26
|style="background:#9f9"| AD[31] ||style="background:#9f9" colspan=2| AD[30] ||rowspan=14 align=left| Address/data bus (upper half)
|-
! 27
|style="background:#9f9"| AD[29] ||style="background:#9f9" colspan=2| AD[28]
|-
! 28
|style="background:silver"| +3.3&nbsp;V ||style="background:silver" colspan=2| +3.3&nbsp;V
|-
! 29
|style="background:#9f9"| AD[27] ||style="background:#9f9" colspan=2| AD[26]
|-
! 30
|style="background:#9f9"| AD[25] ||style="background:#9f9" colspan=2| AD[24]
|-
! 31
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground
|-
! 32
|style="background:#9f9"| AD_STB[1] ||style="background:#9f9" colspan=2| AD_STB[1]#
|-
! 33
|style="background:#9f9"| AD[23] ||style="background:#f9f" colspan=2| C/BE[3]#
|-
! 34
|style="background:silver"| Vddq ||style="background:silver" colspan=2| Vddq
|-
! 35
|style="background:#9f9"| AD[21] ||style="background:#9f9" colspan=2| AD[22]
|-
! 36
|style="background:#9f9"| AD[19] ||style="background:#9f9" colspan=2| AD[20]
|-
! 37
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground
|-
! 38
|style="background:#9f9"| AD[17] ||style="background:#9f9" colspan=2| AD[18]
|-
! 39
|style="background:#f9f"| C/BE[2]# ||style="background:#9f9" colspan=2| AD[16]
|-
! 40
|style="background:silver"| Vddq ||style="background:silver" colspan=2| Vddq ||align=left| 3.3 or 1.5&nbsp;V
|-
! 41
|style="background:#f9f"| IRDY# ||style="background:#f9f" colspan=2| FRAME# ||align=left| Initiator ready, Transfer in progress
|-
! 42
|style="background:silver"| +3.3&nbsp;V aux ||style="background:#ff9" colspan=2| Reserved ||rowspan=4 align=left| Key notch for 1.5&nbsp;V AGP cards
|-
! 43
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground
|-
! 44
|style="background:#ff9"| Reserved ||style="background:#ff9" colspan=2| Reserved
|-
! 45
|style="background:silver"| +3.3&nbsp;V ||style="background:silver" colspan=2| +3.3&nbsp;V
|-
! 46
|style="background:#99f"| DEVSEL# ||style="background:#99f" colspan=2| TRDY# ||align=left| Target selected, Target ready
|-
! 47
|style="background:silver"| Vddq ||style="background:#99f" colspan=2| STOP# ||align=left| Target requests halt
|-
! 48
|style="background:#f69"| PERR# ||style="background:#fc6" colspan=2| PME# ||align=left| Parity error, Power management event (optional)
|-
! 49
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground ||align=left|
|-
! 50
|style="background:#fc6"| SERR# ||style="background:#9f9" colspan=2| PAR ||align=left| System error, Even parity for (1x) PCI transactions only
|-
! 51
|style="background:#f9f"| C/BE[1]# ||style="background:#9f9" colspan=2| AD[15] ||rowspan=15 align=left| Address/data bus (lower half)
|-
! 52
|style="background:silver"| Vddq ||style="background:silver" colspan=2| Vddq
|-
! 53
|style="background:#9f9"| AD[14] ||style="background:#9f9" colspan=2| AD[13]
|-
! 54
|style="background:#9f9"| AD[12] ||style="background:#9f9" colspan=2| AD[11]
|-
! 55
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground
|-
! 56
|style="background:#9f9"| AD[10] ||style="background:#9f9" colspan=2| AD[9]
|-
! 57
|style="background:#9f9"| AD[8] ||style="background:#f9f" colspan=2| C/BE[0]#
|-
! 58
|style="background:silver"| Vddq ||style="background:silver" colspan=2| Vddq
|-
! 59
|style="background:#9f9"| AD_STB[0] ||style="background:#9f9" colspan=2| AD_STB[0]#
|-
! 60
|style="background:#9f9"| AD[7] ||style="background:#9f9" colspan=2| AD[6] 
|-
! 61
|style="background:#999"| Ground ||style="background:#999" colspan=2| Ground
|-
! 62
|style="background:#9f9"| AD[5] ||style="background:#9f9" colspan=2| AD[4] 
|-
! 63
|style="background:#9f9"| AD[3] ||style="background:#9f9" colspan=2| AD[2] 
|-
! 64
|style="background:silver"| Vddq ||style="background:silver" colspan=2| Vddq
|-
! 65
|style="background:#9f9"| AD[1] ||style="background:#9f9" colspan=2| AD[0] 
|-
! 66
|style="background:#66f"| Vregcg ||style="background:#f69" colspan=2| Vrefgc ||align=left| I/O reference voltages
|}

{|class=wikitable
|+Legend
!style="background:#999"| Ground pin
| Zero volt reference
|-
!style="background:silver"| Power pin
| Supplies power to the AGP card
|-
!style="background:#f69"| Output pin
| Driven by the AGP card, received by the motherboard
|-
!style="background:#f9f"| Initiator output
| Driven by the master/initiator, received by the target
|-
!style="background:#9f9"|I/O signal
| May be driven by initiator or target, depending on operation
|-
!style="background:#99f"| Target output
| Driven by the target, received by the initiator/master
|-
!style="background:#66f"| Input
| Driven by the motherboard, received by the AGP card
|-
!style="background:#fc6"| [[Open drain]]
| May be pulled low and/or sensed by card or motherboard
|-
!style="background:#ff9"| Reserved
| Not presently used, do not connect
|}

PCI signals omitted are:
* The −12&nbsp;V supply
* The third and fourth interrupt requests (INTC#, INTD#)
* The [[JTAG]] pins (TRST#, TCK, TMS, TDI, TDO)
* The [[SMBus]] pins (SMBCLK, SMBDAT)
* The IDSEL pin; an AGP card connects AD[16] to IDSEL internally
* The 64-bit extension (REQ64#, ACK64#) and 66&nbsp;MHz (M66EN) pins
* The LOCK# pin for locked transaction support

Signals added are:
* Data strobes AD_STB[1:0] (and AD_STB[1:0]# in AGP 2.0)
* The sideband address bus SBA[7:0] and SB_STB (and SB_STB# in AGP 2.0)
* The ST[2:0] status signals
* USB+ and USB− (and OVERCNT# in AGP 2.0)
* The PIPE# signal (removed in AGP 3.0 for 0.8&nbsp;V signaling)
* The RBF# signal
* The TYPEDET#, Vregcg and Vreggc pins (AGP 2.0 for 1.5V signaling)
* The DBI_HI and DBI_LO signals (AGP 3.0 for 0.8&nbsp;V signaling only)
* The GC_DET# and MB_DET# pins (AGP 3.0 for 0.8V signaling)
* The WBF# signal (AGP 3.0 fast write extension)