Editing PDP-10 (section)

===Interrupt handling===
A second use of the CONO instruction is to set the device's priority level for [[interrupt]] handling. There are three bits in the CONO instruction, 33 through 35, allowing the device to be set to level 0 through 7. Level 1 is the highest, meaning that if two devices raise an interrupt at the same time, the lowest-numbered device will begin processing. Level 0 means "no interrupts", so a device set to level 0 will not stop the processor even if it does raise an interrupt.{{sfn|Programming|1970|p=92}}

Each device channel has two memory locations associated with it, one at 40+2N and the other at 41+2N, where N is the channel number. Thus, channel 1 uses locations 42 and 43. When the interrupt is received and accepted, meaning no higher-priority interrupt is already running, the system stops at the next memory read part of the [[instruction cycle]] and instead begins processing at the address stored in the first of those two locations. It is up to the [[interrupt handler]] to turn off the interrupt level when it is complete, which it can do by running a CONO, DATA or BLK instruction.{{sfn|Programming|1970|p=92}} As a special case, if the instruction is BLKI or BLKO, and the incremented count is not zero, the interrupt is dismissed immediately, otherwise the second instruction is executed to process the interrupt. This provided a low-cost medium performance version of direct memory access.

Two of the device numbers are set aside for special purposes. Device 0 is the computer's front-panel console; reading that device retrieves the settings of the panel switches while writing lights up the status lamps. Device 4 is the "priority interrupt", which can be read using CONI to gain additional information about an interrupt that has occurred.{{sfn|Programming|1970|p=94}}