Editing Motorola 68000 (section)

===Interrupts===<!-- This section is linked from [[Guru Meditation]] -->
The CPU recognizes seven [[interrupt]] levels. Levels 1 through 5 are strictly prioritized. That is, a higher-numbered interrupt can always interrupt a lower-numbered interrupt. In the status register, a privileged instruction allows setting the current minimum interrupt level, blocking lower or equal priority interrupts. For example, if the interrupt level in the status register is set to 3, higher levels from 4 to 7 can cause an exception. Level 7 is a level triggered [[non-maskable interrupt]] (NMI). Level 1 can be interrupted by any higher level. Level 0 means no interrupt. The level is stored in the status register, and is visible to user-level programs.

Hardware interrupts are signalled to the CPU using three inputs that encode the highest pending interrupt priority. A separate encoder is usually required to encode the interrupts, though for systems that do not require more than three hardware interrupts it is possible to connect the interrupt signals directly to the encoded inputs at the cost of more software complexity. The interrupt controller can be as simple as a [[7400-series integrated circuits|74LS148]] priority encoder, or may be part of a [[Very Large Scale Integration|very large-scale integration]] (VLSI) peripheral chip such as the MC68901 Multi-Function Peripheral (used in the [[Atari ST]] range of computers and [[X68000]]), which also provides a [[UART]], timer, and parallel I/O.

The "exception table" ([[interrupt vector table]] interrupt vector addresses) is fixed at addresses 0 through 1023, permitting 256 32-bit vectors. The first vector (RESET) consists of two vectors, namely the starting stack address, and the starting code address. Vectors 3 through 15 are used to report various errors: [[bus error]], address error, [[illegal instruction]], [[zero division]], CHK and CHK2 vector, privilege violation (to block [[privilege escalation]]), and some reserved vectors that became line 1010 emulator, line 1111 emulator, and hardware [[breakpoint]]. Vector 24 starts the '''real''' interrupts: [[spurious interrupt]] (no hardware acknowledgement), and level 1 through level 7 autovectors, then the 16&nbsp;TRAP vectors, then some more reserved vectors, then the user defined vectors.

Since the starting code address vector must always be valid on reset, systems commonly included some nonvolatile memory (e.g. [[Read-only memory|ROM]]) starting at address zero to contain the vectors and [[booting|bootstrap]] code. However, for a general purpose system it is desirable for the operating system to be able to change the vectors at runtime. This was often accomplished by either pointing the vectors in ROM to a [[Branch table|jump table]] in [[Random Access Memory|RAM]], or through use of [[bank switching]] to allow the ROM to be replaced by RAM at runtime.

The 68000 does not meet the [[Popek and Goldberg virtualization requirements]] for full processor virtualization because it has a single unprivileged instruction, "MOVE from SR", which allows user-mode software read-only access to a small amount of privileged state. The 68EC000 and 68SEC000, which are later derivatives of the 68000, do meet the requirements as the "MOVE from SR" instruction is privileged. The same change was introduced on the 68010 and later CPUs.

The 68000 is also unable to easily support [[virtual memory]], which requires the ability to trap and recover from a failed memory access. The 68000 does provide a bus error exception which can be used to trap, but it does not save enough processor state to resume the faulted instruction once the operating system has handled the exception. Several companies did succeed in making 68000-based Unix workstations with virtual memory that worked by using two 68000 chips running in parallel on different phased clocks. When the "leading" 68000 encountered a bad memory access, extra hardware would interrupt the "main" 68000 to prevent it from also encountering the bad memory access. This interrupt routine would handle the virtual memory functions and restart the "leading" 68000 in the correct state to continue properly synchronized operation when the "main" 68000 returned from the interrupt.

These problems were fixed in the next major revision of the 68k architecture with the release of the MC68010. The Bus Error and Address Error exceptions push a large amount of internal state onto the supervisor stack in order to facilitate recovery, and the "MOVE from SR" instruction was made privileged. A new unprivileged "MOVE from CCR" instruction is provided for use in its place by user mode software; an operating system can trap and emulate user mode "MOVE from SR" instructions if desired.