Editing Microcode (section)

==Comparison to VLIW and RISC==
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The design trend toward heavily microcoded processors with complex instructions began in the early 1960s and continued until roughly the mid-1980s. At that point the [[RISC]] design philosophy started becoming more prominent.

A CPU that uses microcode generally takes several clock cycles to execute a single instruction, one clock cycle for each step in the microprogram for that instruction. Some [[Complex instruction set computer|CISC]] processors include instructions that can take a very long time to execute. Such variations interfere with both [[interrupt latency]] and, what is far more important in modern systems, [[Instruction pipelining|pipelining]].

When designing a new processor, a [[hardwired control]] RISC has the following advantages over microcoded CISC:
* Programming has largely moved away from assembly level, so it's no longer worthwhile to provide complex instructions for productivity reasons.
* Simpler instruction sets allow direct execution by hardware, avoiding the performance penalty of microcoded execution.
* Analysis shows complex instructions are rarely used, hence the machine resources devoted to them are largely wasted.
* The machine resources devoted to rarely used complex instructions are better used for expediting performance of simpler, commonly used instructions.
* Complex microcoded instructions may require many clock cycles that vary, and are difficult to [[pipeline (computing)|pipeline]] for increased performance.

There are counterpoints as well:
* The complex instructions in heavily microcoded implementations may not take much extra machine resources, except for microcode space. For example, the same ALU is often used to calculate an effective address and to compute the result from the operands, e.g., the original [[Z80]], [[8086]], and others.
* The simpler non-RISC instructions (i.e., involving direct memory [[operand]]s) are frequently used by modern compilers. Even immediate to stack (i.e., memory result) arithmetic operations are commonly employed. Although such memory operations, often with varying length encodings, are more difficult to pipeline, it is still fully feasible to do so - clearly exemplified by the [[i486]], [[AMD K5]], [[Cyrix 6x86]], [[Motorola 68040]], etc.
* Non-RISC instructions inherently perform more work per instruction (on average), and are also normally highly encoded, so they enable smaller overall size of the same program, and thus better use of limited cache memories.

Many RISC and [[Very long instruction word|VLIW]] processors are designed to execute every instruction (as long as it is in the cache) in a single cycle. This is very similar to the way CPUs with microcode execute one microinstruction per cycle. VLIW processors have instructions that behave similarly to very wide horizontal microcode, although typically without such fine-grained control over the hardware as provided by microcode. RISC instructions are sometimes similar to the narrow vertical microcode.

Microcode has been popular in application-specific processors such as [[network processor]]s, [[digital signal processor]]s, [[Channel I/O|channel controller]]s, [[disk controller]]s, [[network interface controller]]s, [[flash memory controller]]s, [[graphics processing unit]]s, and in other hardware.