Editing MIPS architecture (section)

=== MIPS SIMD architecture (MSA) ===
Instruction set extensions designed to accelerate multimedia.
* 32 vector registers of 16 x 8-bit, 8 x 16-bit, 4 x 32-bit, and 2 x 64 bit vector elements
* Efficient vector parallel arithmetic operations on integer, fixed-point and floating-point data
* Operations on absolute value operands
* Rounding and saturation options available
* Full precision multiply and multiply-add
* Conversions between integer, floating-point, and fixed-point data
* Complete set of vector-level compare and branch instructions with no condition flag
* Vector (1D) and array (2D) shuffle operations
* Typed load and store instructions for [[Endianness|endian]]-independent operation
* IEEE Standard for Floating-Point Arithmetic 754-2008 compliant
* Element precise floating-point exception signaling
* Pre-defined scalable extensions for chips with more gates/transistors
* Accelerates compute-intensive applications in conjunction with leveraging generic compiler support
* Software-programmable solution for consumer electronics applications or functions not covered by dedicated hardware
* Emerging data mining, feature extraction, image and video processing, and human-computer interaction applications
* High-performance scientific computing