Editing Itanium (section)

==== Hewlett-Packard ====
HP has designed four different chipsets for Itanium 2: zx1, sx1000, zx2 and sx2000. All support 4 sockets per chipset, but sx1000 and sx2000 support interconnection of up to 16 chipsets to create up to a 64 socket system. As it was developed in collaboration with Itanium 2's development, booting the first Itanium 2 in February 2001,<ref>{{cite web |title=Overview of the new Itanium® 2-based HP servers rx2600 and rx5670: how HP is putting Intel® Itanium 2 processors to work |url=http://www.hp.com/products1/itanium/infolibrary/whitepapers/5981_2240EN.pdf |page=17 |publisher=Hewlett-Packard |archive-url=https://web.archive.org/web/20030319214329/http://www.hp.com/products1/itanium/infolibrary/whitepapers/5981_2240EN.pdf |archive-date=19 March 2003 |url-status=dead}}</ref> zx1 became the first Itanium 2 chipset available and later in 2004 also the first to support 533 MT/s FSB. In its basic two-chip version it directly provides four channels of [[DDR SDRAM|DDR-266]] memory, giving 8.5 GB/s of bandwidth and 32 GB of capacity (though 12 DIMM slots).<ref>{{cite web |title=HP Integrity rx2620 Server |url=http://h18000.www1.hp.com/products/quickspecs/12141_div/12141_div.PDF |archive-url=https://web.archive.org/web/20061029145359/http://h18000.www1.hp.com/products/quickspecs/12141_div/12141_div.PDF |archive-date=29 October 2006 |url-status=dead}}</ref> In versions with memory expander boards memory bandwidth reaches 12.8 GB/s, while the maximum capacity for the initial two-board 48 DIMM expanders was 96 GB, and the later single-board 32 DIMM expander up to 128 GB. The memory latency increases by 25 nanoseconds from 80 ns due to the expanders. Eight independent links went to the PCI-X and other peripheral devices (e.g. [[Accelerated Graphics Port|AGP]] in workstations), totaling 4 GB/s.<ref>{{cite web |title=HP Integrity rx4640-8 Server |url=http://h18000.www1.hp.com/products/quickspecs/11847_div/11847_div.PDF |archive-url=https://web.archive.org/web/20060314004913/http://h18000.www1.hp.com/products/quickspecs/11847_div/11847_div.PDF |archive-date=14 March 2006 |url-status=dead}}</ref><ref>{{cite web |title=HP Integrity rx5670 Server summary |url=http://www.hp.com/products1/servers/integrity/entry_level/rx5670/index.html |archive-url=https://web.archive.org/web/20041209002029/http://www.hp.com/products1/servers/integrity/entry_level/rx5670/index.html |archive-date=9 December 2004 |url-status=dead}}</ref>

HP's first high-end Itanium chipset was sx1000, launched in mid-2003 with the [[HP Superdome|Integrity Superdome]] flagship server.
It has two independent front-side buses, each bus supporting two sockets, giving 12.8 GB/s of combined bandwidth from the processors to the chipset. It has four links to data-only memory buffers and supports 64 GB of HP-designed 125&nbsp;MHz memory at 16 GB/s. The above components form a system board called a ''cell''. Two cells can be directly connected together to create an 8-socket [[Glue logic|glue]]less system. To connect four cells together, a pair of 8-ported [[crossbar switch]]es is needed (adding 64 [[Nanosecond|ns]] to inter-cell memory accesses), while four such pairs of crossbar switches are needed for the top-end system of 16 cells (64 sockets), giving 32 GB/s of [[bisection bandwidth]]. Cells maintain cache coherence through in-memory [[Directory-based cache coherence|directories]], which causes the minimum memory latency to be 241 ns. The latency to the most remote ([[Non-uniform memory access|NUMA]]) memory is 463 ns. The per-cell bandwidth to the I/O subsystems is 2 GB/s, despite the presence of 8 GB/s worth of PCI-X buses in each I/O subsystem.<ref>{{cite web |last1=Turner |first1=Vernon |last2=Rau |first2=Shane |title=HP's sx1000 Chipset: Innovation Atop Standardization |url=http://h71028.www7.hp.com/ERC/downloads/sx1000_White_Paper_.pdf |publisher=[[International Data Group|IDC]] (sponsored by HP) |archive-url=https://web.archive.org/web/20050601104604/http://h71028.www7.hp.com/ERC/downloads/sx1000_White_Paper_.pdf |archive-date=1 June 2005 |url-status=dead}}</ref><ref>{{cite web |title=Meet the HP Integrity Superdome: A white paper from HP |url=http://www.hp.com/products1/servers/integrity/superdome_high_end/infolibrary/Superdome_wp.pdf |archive-url=https://web.archive.org/web/20040731205815/http://www.hp.com/products1/servers/integrity/superdome_high_end/infolibrary/Superdome_wp.pdf |archive-date=31 July 2004 |url-status=dead}}</ref><ref>{{cite web |title=Itanium®–based midrange servers from HP— the HP Integrity rx7620-16 and rx8620-32 Servers |url=http://h21007.www2.hp.com/dspp/files/unprotected/integritymidrangejan05.pdf |archive-url=https://web.archive.org/web/20050509234702/http://h21007.www2.hp.com/dspp/files/unprotected/integritymidrangejan05.pdf |archive-date=9 May 2005 |url-status=dead}}</ref>

HP launched sx2000 in March 2006 to succeed sx1000. Its two FSBs operate at 533 MT/s. It supports up to 128 GB of memory at 17 GB/s. The memory is of HP's custom design, using the [[DDR2 SDRAM|DDR2]] protocol, but twice as tall as the standard modules and with redundant address and control signal contacts. For the inter-chipset communication, 25.5 GB/s is available on each sx2000 through its three [[Serial communication|serial]] links that can connect to a set of three [[Redundancy (engineering)|independent]] [[Crossbar switch|crossbars]], which connect to other cells or up to 3 other sets of 3 crossbars. The multi-cell configurations are the same as with sx1000, except the parallelism of the sets of crossbars has been increased from 2 to 3. The maximum configuration of 64 sockets has 72 GB/s of sustainable [[bisection bandwidth]]. The chipset's connection to its I/O module is now serial with an 8.5 GB/s peak and 5.5 GB/s sustained bandwidth, the I/O module having either 12 [[PCI-X]] buses at up to 266&nbsp;MHz, or 6 PCI-X buses and 6 [[PCIe]] 1.1 ×8 slots. It is the last chipset to support HP's [[PA-RISC]] processors ([[PA-8000#PA-8900|PA-8900]]).<ref>{{Cite web|url=http://archive.org/details/manualzilla-id-7031299|title=User Service Guide HP Integrity Superdome/sx2000 and HP 9000 Superdome/sx2000 Servers|publisher=[[Hewlett-Packard]]|date=September 2009|via=Internet Archive}}</ref>

HP launched the first zx2-based servers in September 2006. zx2 can operate the FSB at 667 MT/s with two CPUs or 533 MT/s with four CPUs. It connects to the [[DDR2 SDRAM|DDR2]] memory either directly, supporting 32 GB at up to 14.2 GB/s, or through expander boards, supporting up to 384 GB at 17 GB/s. The minimum open-page latency is 60 to 78 ns. 9.8 GB/s are available through eight independent links to the I/O adapters, which can include PCIe ×8 or 266&nbsp;MHz PCI-X.<ref>{{cite web |title=Overview of the HP Integrity rx2660, rx3600, and rx6600 Servers |url=https://shoredata.us.com/wp-content/uploads/2016/03/rx6600.pdf |archive-url=https://web.archive.org/web/20170306041015/https://shoredata.us.com/wp-content/uploads/2016/03/rx6600.pdf |archive-date=2017-03-06 |url-status=live}}</ref><ref>{{cite web |title=HP Integrity systems Family guide |url=https://www.hp.com/ch-de/pdf/harness_family_brosch_re_4aa3-4519enw_tcm_179_1247486.pdf |access-date=24 May 2022|archive-url=https://web.archive.org/web/20220708214847/https://www.hp.com/ch-de/pdf/harness_family_brosch_re_4aa3-4519enw_tcm_179_1247486.pdf|archive-date=8 July 2022|url-status=dead}}</ref>