Editing ARM architecture family (section)

===CPU modes===
Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes, depending on the implemented architecture features. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically.<ref name="Chdddhea">{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Chdddhea.html |title=Processor mode |publisher=[[Arm Holdings]] |access-date=26 March 2013}}</ref>
* ''User mode:'' The only non-privileged mode.
* ''FIQ mode:'' A privileged mode that is entered whenever the processor accepts a [[fast interrupt request]].
* ''IRQ mode:'' A privileged mode that is entered whenever the processor accepts an interrupt.
* ''Supervisor (svc) mode:'' A privileged mode entered whenever the CPU is reset or when an SVC instruction is executed.
* ''Abort mode:'' A privileged mode that is entered whenever a prefetch abort or data abort exception occurs.
* ''Undefined mode:'' A privileged mode that is entered whenever an undefined instruction exception occurs.
* ''System mode (ARMv4 and above):'' The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the Current Program Status Register (CPSR) from another privileged mode (not from user mode).
* ''Monitor mode (ARMv6 and ARMv7 Security Extensions, ARMv8 EL3):'' A monitor mode is introduced to support TrustZone extension in ARM cores.
* ''Hyp mode (ARMv7 Virtualization Extensions, ARMv8 EL2):'' A hypervisor mode that supports [[Popek and Goldberg virtualization requirements]] for the non-secure operation of the CPU.<ref name="2012-lpc-arm-zyngier">{{cite web |url=https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-arm-zyngier.pdf |title=KVM/ARM |access-date=14 February 2023}}</ref><ref>{{cite conference |title=Extensions to the ARMv7-A Architecture |first=David |last=Brash |conference=2010 IEEE Hot Chips 22 Symposium (HCS) |date=August 2010 |pages=1–21 |doi=10.1109/HOTCHIPS.2010.7480070 |isbn=978-1-4673-8875-7 |s2cid=46339775 }}</ref>
* ''Thread mode (ARMv6-M, ARMv7-M, ARMv8-M):'' A mode which can be specified as either privileged or unprivileged. Whether the Main Stack Pointer (MSP) or Process Stack Pointer (PSP) is used can also be specified in CONTROL register with privileged access. This mode is designed for user tasks in RTOS environment but it is typically used in bare-metal for super-loop.
* ''Handler mode (ARMv6-M, ARMv7-M, ARMv8-M):'' A mode dedicated for exception handling (except the RESET which are handled in Thread mode). Handler mode always uses MSP and works in privileged level.