Editing X86 (section)

===Miscellaneous/special purpose===
x86 processors that have a [[protected mode]], i.e. the 80286 and later processors, also have three descriptor registers (GDTR, LDTR, [[Interrupt descriptor table|IDTR]]) and a task register (TR).

32-bit x86 processors (starting with the 80386) also include various special/miscellaneous registers such as [[control register]]s (CR0 through 4, CR8 for 64-bit only), [[debug register]]s (DR0 through 3, plus 6 and 7), [[test register]]s (TR3 through 7; 80486 only), and [[model-specific register]]s (MSRs, appearing with the Pentium{{Efn|Two MSRs of particular interest are SYSENTER_EIP_MSR<!-- (0x176) --> and SYSENTER_ESP_MSR<!-- (0x175) -->, introduced on the Pentium® II processor, which store the address of the kernel mode system service handler<!-- nt!KiFastCallEntry --> and corresponding kernel stack pointer. Initialized during system startup, SYSENTER_EIP_MSR and SYSENTER_ESP_MSR are used by the SYSENTER (Intel) or SYSCALL (AMD) instructions to achieve Fast System Calls, about three times faster<!-- http://www.codeguru.com/cpp/misc/misc/system/article.php/c8223/System-Call-Optimization-with-the-SYSENTER-Instruction.htm 266% as fast (166% faster) on a PIII Dual 800 MHz --> than the software interrupt method used previously.}}).

[[AVX-512]] has eight extra 64-bit mask registers K0–K7 for selecting elements in a vector register. Depending on the vector register and element widths, only a subset of bits of the mask register may be used by a given instruction.