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Synchronous dynamic random-access memory
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=== SDR === [[Image:Micron 48LC32M8A2-AB.jpg|thumb|upright=1.25|The 64 MB{{binpre}} of sound memory on the [[Sound Blaster X-Fi|Sound Blaster X-Fi Fatality Pro]] [[sound card]] is built from 2 [[Micron Technology|Micron]] 48LC32M8A2 SDRAM chips. They run at 133 MHz (7.5 ns clock period) and have 8-bit wide data buses.<!-- x8 3.3V TSOP-54 CL=3 PC133 --><ref>{{cite web|title=SDRAM Part Catalog|url=http://www.micron.com/products/dram/sdram/partlist}} 070928 micron.com</ref>]] Originally simply known as ''SDRAM'', single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin [[DIMM]]s that read or write 64 (non-ECC) or 72 ([[ECC memory|ECC]]) bits at a time. Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time. Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns), respectively denoted PC66, PC100, and PC133. Clock rates up to 200 MHz were available. It operates at a voltage of 3.3 V. This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate). But this type is also faster than its predecessors [[extended data out DRAM]] (EDO-RAM) and [[fast page mode DRAM]] (FPM-RAM) which took typically two or three clocks to transfer one word of data. ==== PC66 ==== '''PC66''' refers to internal removable computer [[random-access memory|memory]] standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC66 is Synchronous DRAM operating at a clock frequency of 66.66 MHz, on a 64-bit bus, at a voltage of 3.3 V. PC66 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. The theoretical bandwidth is 533 MB/s. (1 MB/s = one million bytes per second) This standard was used by [[Original Intel Pentium (P5 microarchitecture)|Intel Pentium]] and [[AMD K6]]-based PCs. It also features in the Beige [[Power Mac G3]], early [[iBook]]s and [[PowerBook G3]]s. It is also used in many early [[Intel Celeron]] systems with a 66 MHz [[front-side bus|FSB]]. It was superseded by the PC100 and PC133 standards. ==== PC100 ==== {{For|the Japanese home computer|NEC PC-100}} [[Image:SDRAM 128MB 133MHz.jpg|thumb|upright=1.25|DIMM: 168 pins and two notches]] '''PC100''' is a standard for internal removable computer [[random-access memory]], defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] [[Computer form factor|form factor]]s. PC100 is [[backward compatible]] with PC66 and was superseded by the PC133 standard. A module built out of 100 MHz SDRAM chips is not necessarily capable of operating at 100 MHz. The PC100 standard specifies the capabilities of the [[memory module]] as a whole. PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory. ==== PC133 ==== '''PC133''' is a computer memory standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC133 refers to [[SDR SDRAM]] operating at a clock frequency of 133 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC133 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066 GB per second ([133.33 MHz * 64/8]=1.066 GB/s). (1 GB/s = one billion bytes per second) PC133 is [[backward compatible]] with PC100 and PC66.
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