Editing Phase-locked loop (section)

==Block diagram==
[[File:PLL generic inline optional N.svg|center|thumb|550x550px|[[Block diagram]] of a phase-locked loop]]
The block diagram shown in the figure shows an input signal, ''F''<sub>''I''</sub>, which is used to generate an output, ''F''<sub>''O''</sub>. The input signal is often called the ''reference signal'' (also abbreviated ''F''<sub>''REF''</sub>).<ref>{{cite journal |last1=Collins |first1=Ian |date=July 2018 |title=Phase-Locked Loop (PLL) Fundamentals |url=https://www.analog.com/en/analog-dialogue/articles/phase-locked-loop-pll-fundamentals.html |journal=Analog Dialogue |volume=52 |archive-url=https://web.archive.org/web/20180714000017/https://www.analog.com/en/analog-dialogue/articles/phase-locked-loop-pll-fundamentals.html |archive-date=2018-07-14}}</ref>

At the input, a phase detector (shown as the [[Phase detector#Phase frequency detector|Phase frequency detector]] and [[Charge pump]] blocks in the figure) compares two input signals, producing an error signal which is proportional to their phase difference. The error signal is then low-pass filtered and used to drive a VCO which creates an output phase. The output is fed through an optional divider back to the input of the system, producing a [[negative feedback loop]]. If the output phase drifts, the error signal will increase, driving the VCO phase in the opposite direction so as to reduce the error. Thus the output phase is locked to the phase of the input.

Analog phase locked loops are generally built with an analog phase detector, low-pass filter and VCO placed in a [[negative feedback]] configuration. A digital phase locked loop uses a digital phase detector; it may also have a divider in the feedback path or in the reference path, or both, in order to make the PLL's output signal frequency a [[Rational number|rational]] multiple of the reference frequency. A non-integer multiple of the reference frequency can also be created by replacing the simple divide-by-''N'' counter in the feedback path with a programmable [[pulse swallowing counter]]. This technique is usually referred to as a [[fractional-N synthesizer]] or fractional-N PLL.{{dubious|date=December 2010}}<!-- doesn't fractional-N also adjust the phase at the phase detector. otherwise there's a error signal. -->

The oscillator generates a periodic output signal. Assume that initially the oscillator is at nearly the same frequency as the reference signal. If the phase from the oscillator falls behind that of the reference, the phase detector changes the control voltage of the oscillator so that it speeds up. Likewise, if the phase creeps ahead of the reference, the phase detector changes the control voltage to slow down the oscillator. Since initially the oscillator may be far from the reference frequency, practical phase detectors may also respond to frequency differences, so as to increase the lock-in range of allowable inputs. Depending on the application, either the output of the controlled oscillator, or the control signal to the oscillator, provides the useful output of the PLL system.{{citation needed|date=October 2017}}