Editing MIPS architecture (section)

=== MIPS Digital Signal Processing (DSP) ===
The DSP ASE is an optional extension to the MIPS32/MIPS64 Release&nbsp;2 and newer instruction sets which can be used to accelerate a large range of "media" computations—particularly audio and video. The DSP module comprises a set of instructions and state in the integer pipeline and requires minimal additional logic to implement in MIPS processor cores. Revision 2 of the ASE was introduced in the second half of 2006. This revision adds extra instructions to the original ASE, but is otherwise backwards-compatible with it.<ref>{{cite web|url=https://gcc.gnu.org/onlinedocs/gcc/MIPS-DSP-Built-in-Functions.html|title=Using the GNU Compiler Collection (GCC): MIPS DSP Built-in Functions|website=gcc.gnu.org|url-status=live|archive-url=https://web.archive.org/web/20170420143138/https://gcc.gnu.org/onlinedocs/gcc/MIPS-DSP-Built-in-Functions.html|archive-date=April 20, 2017}}</ref> Unlike the bulk of the MIPS architecture, it's a fairly irregular set of operations, many chosen for a particular relevance to some key algorithm. Its main novel features (vs original MIPS32):<ref>{{cite web|url=https://www.linux-mips.org/wiki/Instruction_Set_Architecture#DSP_ASE|title=Instruction Set Architecture - LinuxMIPS|website=www.linux-mips.org|url-status=dead|archive-url=https://web.archive.org/web/20170420045837/https://www.linux-mips.org/wiki/Instruction_Set_Architecture#DSP_ASE|archive-date=April 20, 2017}}</ref>
* Saturating arithmetic (when a calculation overflows, deliver the representable number closest to the non-overflowed answer).
* Fixed-point arithmetic on signed 32- and 16-bit fixed-point fractions with a range of -1 to +1 (these are widely called "Q31" and "Q15").
* The existing integer multiplication and multiply-accumulate instructions, which deliver results into a double-size accumulator (called "hi/lo" and 64 bits on MIPS32 CPUs). The DSP ASE adds three more accumulators, and some different flavours of multiply-accumulate.
* [[Single instruction, multiple data|SIMD]] instructions operating on 4 x unsigned bytes or 2 x 16-bit values packed into a 32-bit register (the 64-bit variant of the DSP ASE supports larger vectors, too).
* SIMD operations are basic arithmetic, shifts and some multiply-accumulate type operations.