Editing Flash memory (section)

====Structure====
V-NAND uses a [[charge trap flash]] geometry (which was commercially introduced in 2002 by [[AMD]] and [[Fujitsu]])<ref name="auto3"/> that stores charge on an embedded [[silicon nitride]] film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps a planar charge trap cell into a cylindrical form.<ref name="vnand" /> As of 2020, 3D NAND flash memories by Micron and Intel instead use floating gates, however, Micron 128 layer and above 3D NAND memories use a conventional charge trap structure, due to the dissolution of the partnership between Micron and Intel. Charge trap 3D NAND flash is thinner than floating gate 3D NAND. In floating gate 3D NAND, the memory cells are completely separated from one another, whereas in charge trap 3D NAND, vertical groups of memory cells share the same silicon nitride material.<ref name="anandtech-20201109">{{Cite news |last=Tallis |first=Billy |date=9 November 2020 |title=Micron Announces 176-layer 3D NAND |work=[[AnandTech]] |url=https://www.anandtech.com/show/16230/micron-announces-176layer-3d-nand |url-status=live |archive-url=https://web.archive.org/web/20231102133017/https://www.anandtech.com/show/16230/micron-announces-176layer-3d-nand |archive-date=2 November 2023 }}</ref> <!--the exact details of the V-NAND structure vary by manufacturer.-->

An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel.<ref name="vnand" />

Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer. The vertical collection is electrically identical to the serial-linked groups in which conventional NAND&nbsp;flash memory is configured.<ref name="vnand" /> There is also string stacking, which builds several 3D NAND memory arrays or "plugs"<ref>{{Cite web|url=https://blocksandfiles.com/2023/08/18/samsung-has-300-layer-nand-coming-with-430-layers-after-that/|title=Samsung has 300-layer NAND coming, with 430 layers after that – report|first=Chris|last=Mellor|date=18 August 2023}}</ref> separately, but stacked together to create a product with a higher number of 3D NAND layers on a single die. Often, two or 3 arrays are stacked. The misalignment between plugs is in the order of 30 to 10nm.<ref name="auto8"/><ref>{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/9282426|title=2020 China Semiconductor Technology International Conference (CSTIC)|doi=10.1109/CSTIC49141.2020.9282426 |chapter=Manufacturing Challenges and Cost Evaluation of New Generation 3D Memories |date=2020 |last1=Dube |first1=Belinda Langelihle |pages=1–3 |isbn=978-1-7281-6558-5 |s2cid=229376195 }}</ref><ref name="auto9">{{Cite web |last=Choe |first=Jeongdong |date=2019 |title=Comparison of Current 3D NAND Chip & Cell Architecture |url=https://files.futurememorystorage.com/proceedings/2019/08-07-Wednesday/20190807_FTEC-202-1_Choe.pdf |pages=21, 24}}</ref>