Jump to content
Main menu
Main menu
move to sidebar
hide
Navigation
Main page
Recent changes
Random page
Help about MediaWiki
Special pages
Niidae Wiki
Search
Search
Appearance
Create account
Log in
Personal tools
Create account
Log in
Pages for logged out editors
learn more
Contributions
Talk
Editing
Central processing unit
(section)
Page
Discussion
English
Read
Edit
View history
Tools
Tools
move to sidebar
hide
Actions
Read
Edit
View history
General
What links here
Related changes
Page information
Appearance
move to sidebar
hide
Warning:
You are not logged in. Your IP address will be publicly visible if you make any edits. If you
log in
or
create an account
, your edits will be attributed to your username, along with other benefits.
Anti-spam check. Do
not
fill this in!
===Clockless CPUs=== Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and [[heat dissipation]] in comparison with similar synchronous designs. While somewhat uncommon, entire [[Asynchronous circuit#Asynchronous CPU|asynchronous CPUs]] have been built without using a global clock signal. Two notable examples of this are the [[ARM architecture family|ARM]] compliant [[AMULET microprocessor|AMULET]] and the [[MIPS architecture|MIPS]] R3000 compatible MiniMIPS.<ref name=":2">{{Cite journal |last1=Martin |first1=A. J. |last2=Nystrom |first2=M. |last3=Wong |first3=C. G. |date=November 2003 |title=Three generations of asynchronous microprocessors |url=https://ieeexplore.ieee.org/document/1246159 |url-status=live |journal=IEEE Design & Test of Computers |volume=20 |issue=6 |pages=9β17 |doi=10.1109/MDT.2003.1246159 |issn=0740-7475 |s2cid=15164301 |archive-url=https://web.archive.org/web/20211203174748/https://ieeexplore.ieee.org/document/1246159/ |archive-date=2021-12-03 |access-date=2022-01-05}}</ref> Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous [[Arithmetic logic unit|ALUs]] in conjunction with superscalar pipelining to achieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for [[embedded computer]]s.<ref>{{cite conference |author1=Garside, J. D. |author2=Furber, S. B. |author3= Chung, S-H | title = AMULET3 Revealed | publisher = [[University of Manchester]] Computer Science Department | year = 1999 | url = http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php |book-title=Proceedings, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems |doi=10.1109/ASYNC.1999.761522 | archive-url=https://web.archive.org/web/20051210205845/http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php | archive-date=December 10, 2005 | url-status=dead}}</ref>
Summary:
Please note that all contributions to Niidae Wiki may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see
Encyclopedia:Copyrights
for details).
Do not submit copyrighted work without permission!
Cancel
Editing help
(opens in new window)
Search
Search
Editing
Central processing unit
(section)
Add topic