Editing Static random-access memory (section)

==Design==
[[File:SRAM Cell (6 Transistors).svg|thumb|A six-transistor (6T) CMOS SRAM cell. WL: word line. BL: bit line.]]
A typical SRAM cell is made up of six [[MOSFET]]s, and is often called a '''{{abbr|6T|6 transistor}} SRAM cell'''. Each [[bit]] in the cell is stored on four [[transistor]]s (M1, M2, M3, M4) that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional ''access'' transistors serve to control the access to a storage cell during read and write operations. 6T SRAM is the most common kind of SRAM.<ref name="auto">{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/10134887|chapter=A Review of Low-Power Static Random Access Memory (SRAM) Designs |doi=10.1109/DevIC57758.2023.10134887 |s2cid=258984439 |title=2023 IEEE Devices for Integrated Circuit (DevIC) |date=2023 |last1=Rathi |first1=Neetu |last2=Kumar |first2=Anil |last3=Gupta |first3=Neeraj |last4=Singh |first4=Sanjay Kumar |pages=455–459 |isbn=979-8-3503-4726-5 }}</ref> In addition to 6T SRAM, other kinds of SRAM use 4, 5, 7,<ref>{{Cite book|url=https://books.google.com/books?id=rMsqBgAAQBAJ&dq=5+transistor+sram&pg=SA1-PA35|title=The VLSI Handbook|first=Wai-Kai|last=Chen|date=October 3, 2018|publisher=CRC Press|isbn=978-1-4200-0596-7 |via=Google Books}}</ref> 8, 9,<ref name="auto"/> 10<ref>{{Cite journal |doi = 10.1109/JSSC.2007.897148|bibcode = 2007IJSSC..42.2303K|title = A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM|last1 = Kulkarni|first1 = Jaydeep P.|last2 = Kim|first2 = Keejong|last3 = Roy|first3 = Kaushik|journal = IEEE Journal of Solid-State Circuits|volume = 42|issue = 10|pages = 2303|year = 2007|s2cid = 699469}}</ref> (4T, 5T, 7T 8T, 9T, 10T SRAM), or more transistors per bit.<ref>{{cite web | url=https://ieeexplore.ieee.org/document/5770728 | title=0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM  | date=March 2011 | pages=1–4 | doi=10.1109/ISQED.2011.5770728 | s2cid=6397769 }}</ref><ref>United States Patent 6975532: [https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20051213&DB=EPODOC&locale=en_EP&CC=US&NR=6975532B1&KC=B1&ND=4 Quasi-static random access memory]{{Dead link|date=September 2024 |bot=InternetArchiveBot |fix-attempted=yes }}</ref><ref>{{Cite web | url=http://ietele.oxfordjournals.org/cgi/content/abstract/E90-C/10/1949 | title=Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes -- MORITA et al. E90-C (10): 1949 -- IEICE Transactions on Electronics| url-status=dead | archive-url=https://web.archive.org/web/20081205085037/http://ietele.oxfordjournals.org/cgi/content/abstract/E90-C/10/1949| archive-date=2008-12-05}}</ref> Four-transistor SRAM is quite common in stand-alone SRAM devices (as opposed to SRAM used for CPU caches), implemented in special processes with an extra layer of [[polysilicon]], allowing for very high-resistance pull-up resistors.<ref>{{cite book |last1=Preston |first1=Ronald P. |chapter=14: Register Files and Caches |chapter-url=http://courses.engr.illinois.edu/ece512/Papers/Preston_2001_CBF.pdf |year=2001 |title=The Design of High Performance Microprocessor Circuits |publisher=IEEE Press |page=290 |access-date=2013-02-01 |archive-date=2013-05-09 |archive-url=https://web.archive.org/web/20130509010902/http://courses.engr.illinois.edu/ece512/Papers/Preston_2001_CBF.pdf |url-status=dead }}</ref> The principal drawback of using 4T SRAM is increased [[CMOS#Power: switching and leakage|static power]] due to the constant current flow through one of the pull-down transistors (M1 or M2).

[[File:SRAM Cell (4 Transistors).svg|thumb|Four-transistor (4T) SRAM provides advantages in density at the cost of manufacturing complexity. The resistors must have small dimensions and large values.]]

This is sometimes used to implement more than one (read and/or write) port, which may be useful in certain types of [[video memory]] and [[register file]]s implemented with multi-ported SRAM circuitry.

Generally, the fewer transistors needed per cell, the smaller each cell can be. Since the cost of processing a silicon wafer is relatively fixed, using smaller cells and so packing more bits on one wafer reduces the cost per bit of memory.

Memory cells that use fewer than four transistors are possible; however, such 3T<ref>United States Patent 6975531: [http://www.freepatentsonline.com/6975531.html 6F2 3-transistor DRAM gain cell]</ref><ref>[https://tezzaron.com/3t-iram/ 3T-iRAM(r) Technology]</ref> or 1T cells are DRAM, not SRAM (even the so-called [[1T-SRAM]]).

Access to the cell is enabled by the word line (WL in figure) which controls the two ''access'' transistors M<sub>5</sub> and M<sub>6</sub> in 6T SRAM figure (or M<sub>3</sub> and M<sub>4</sub> in 4T SRAM figure) which, in turn, control whether the cell should be connected to the bit lines: <span style="text-decoration: overline;">BL</span> and BL. They are used to transfer data for both read and write operations. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve [[noise margin]]s and speed.

During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM bandwidth compared to DRAMs{{snd}} in a DRAM, the bit line is connected to storage capacitors and [[charge sharing]] causes the bit line to swing upwards or downwards. The symmetric structure of SRAMs also allows for [[differential signaling]], which makes small voltage swings more easily detectable. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.

The size of an SRAM with {{mvar|m}} address lines and {{mvar|n}} data lines is {{math|2<sup>''m''</sup>}} words, or {{math|2<sup>''m''</sup>&nbsp;× ''n''}} bits.  The most common word size is 8 bits, meaning that a single byte can be read or written to each of {{math|2<sup>''m''</sup>}} different words within the SRAM chip.  Several common SRAM chips have 11 address lines (thus a capacity of {{math|2<sup>11</sup> {{=}} 2,048 {{=}}}} 2[[kibi (binary prefix)|k]] words) and an 8-bit word, so they are referred to as ''2k&nbsp;× 8 SRAM''.

The dimensions of an SRAM cell on an IC is determined by the [[minimum feature size]] of the process used to make the IC.
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