Editing Peripheral Component Interconnect (section)

==PCI bus bridges==
The PCI standard permits multiple independent PCI buses to be connected by bus bridges that will forward operations on one bus to another when required. Although PCI tends not to use many bus bridges, [[PCI Express]] systems use many PCI-to-PCI bridge usually called ''PCI Express Root Port''; each PCI Express slot appears to be a separate bus, connected by a bridge to the others. The PCI host bridge (usually [[northbridge (computing)|northbridge]] in x86 platforms) interconnect between CPU, main memory and PCI bus.<ref>{{Cite web|title=Bus Specifics - Writing Device Drivers for Oracle® Solaris 11.3|url=https://docs.oracle.com/cd/E53394_01/html/E54850/hwovr-25520.html|access-date=2020-12-18|website=docs.oracle.com}}</ref>

===Posted writes===
Generally, when a bus bridge sees a transaction on one bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready. One notable exception occurs in the case of memory writes. Here, the bridge may record the write data internally (if it has room) and signal completion of the write before the forwarded write has completed. Or, indeed, before it has begun. Such "sent but not yet arrived" writes are referred to as "posted writes", by analogy with a postal mail message. Although they offer great opportunity for performance gains, the rules governing what is permissible are somewhat intricate.<ref name=bridge11>PCI-to-PCI Bridge Architecture Specification, revision 1.1</ref>

===Combining, merging, and collapsing===
The PCI standard permits bus bridges to convert multiple bus transactions into one larger transaction under certain situations. This can improve the efficiency of the PCI bus.

====Combining====
Write transactions to consecutive addresses may be combined into a longer burst write, as long as the order of the accesses in the burst is the same as the order of the original writes.  It is permissible to insert extra data phases with all byte enables turned off if the writes are almost consecutive.

====Merging====
Multiple writes to disjoint portions of the same word may be merged into a single write with multiple byte enables asserted.  In this case, writes that were presented to the bus bridge in a particular order are merged so they occur at the same time when forwarded.

====Collapsing====
Multiple writes to the same byte or bytes may ''not'' be combined, for example, by performing only the second write and skipping the first write that was overwritten.  This is because the PCI specification permits writes to have side effects.