Editing Pentium Pro (section)

==References==
{{Reflist|30em|refs=

<ref name="Fisher_19951102">{{cite news |last1=Fisher |first1=Lawrence M. |date=November 2, 1995 |title=Intel Offers Its Pentium Pro For Work Station Market |url=https://www.nytimes.com/1995/11/02/business/intel-offers-its-pentium-pro-for-work-station-market.html |url-status=live |url-access=subscription |work=[[The New York Times]] |language=en-us |edition=New York |page=D-2 |eissn=1553-8095 |issn=0362-4331 |archive-url=https://web.archive.org/web/20090804001226/https://www.nytimes.com/1995/11/02/business/intel-offers-its-pentium-pro-for-work-station-market.html |archive-date=August 4, 2009 |access-date=December 28, 2022 |quote=The Intel Corporation today introduced its new microprocessor, the Pentium Pro. But although the chip's performance is higher than expected, and its price lower, analysts said its immediate impact was not likely to match that of its predecessor, the Pentium. |df=dmy-all }}</ref>

<ref name="Brey_2003">{{cite book |last1=Brey |first1=Barry B. |date=2003 |chapter=Introduction to the Microprocessor and Computer |chapter-url=https://archive.org/details/intelmicroproces0000brey_x6t8/page/1 |chapter-url-access=registration |title=The Intel Microprocessors 8086/8088, 80186, 80286, 80386, 80486: Architecture, Programming, and Interfacing |url=https://archive.org/details/intelmicroproces0000brey_x6t8/page/1 |url-access=registration |edition=Sixth (International) |publisher=[[Pearson Education]] |page=12 |isbn=978-0130487209 |lccn=93021801 |oclc=224097450 |ol=OL1412841M |access-date=December 15, 2022 |df=dmy-all }}</ref>

<ref name="ASCI_Red">{{cite web |url=https://www.top500.org/resources/top-systems/asci-red-sandia-national-laboratory/ |date=n.d. |title=ASCI Red: Sandia National Laboratory |website=[[TOP500]] |access-date=January 7, 2023 |quote=Intel’s ASCI Red supercomputer was the first teraflop/s computer, taking the No.1 spot on the 9th TOP500 list in June 1997 with a Linpack performance of 1.068 teraflop/s. [...] It was a mesh-based (38 X 32 X 2) MIMD massively parallel machine initially consisting of 7,264 compute nodes, 1,212 gigabytes of total distributed memory and 12.5 terabytes of disk storage. The original incarnation of this machine used Intel Pentium Pro processors, each clocked at 200 MHz. These were later upgraded to Pentium II OverDrive processors. The system was upgraded to a total of 9,632 Pentium II Over-Drive processors, each clocked at 333 MHz. |archive-date=January 7, 2023 |archive-url=https://web.archive.org/web/20230107213536/https://www.top500.org/resources/top-systems/asci-red-sandia-national-laboratory/ |url-status=live }}</ref>

<ref name="dvorak">{{cite web |url=http://www.dvorak.org/blog/whatever-happened-to-the-intel-iapx432/ |date=November 25, 2006 |title=Whatever Happened to The iAPX432 – Intel's Dream Chip? |last1=Dvorak |first1=John C. |author-link1=John C. Dvorak |website=Dvorak Uncensored |access-date=December 28, 2022 |archive-url=https://web.archive.org/web/20081213193013/http://www.dvorak.org/blog/whatever-happened-to-the-intel-iapx432/ |language=en-us |archive-date=December 13, 2008 |url-status=live |quote=There were a lot of pieces involved in this chip but today’s Pentium Pro consists of two chips and other needed support chips too. Curiously the lead engineer for the 432 was superstar designer Fred Pollack who became the lead architect for the Pentium Pro. |df=dmy-all}}</ref>

<ref name="Stiller_1996">{{cite magazine |last1=Stiller |first1=Andreas |last2=Paul |first2=Matthias R. <!-- contributor on processor internals --> |date=May 12, 1996 |title=Trends & News {{!}} Prozessorgeflüster |trans-title=Trends & News {{!}} Processor whisper |url=https://www.heise.de/blog/Prozessorgefluester-284546.html <!-- old url https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html --> |url-access=subscription |url-status=live |magazine=[[c't|c't {{!}} magazin für computertechnik]] |language=de |publisher=[[Heinz Heise]] |issn=0724-8679 |oclc=314471122 |archive-url=https://web.archive.org/web/20221228162604/https://www.heise.de/blog/Prozessorgefluester-284546.html <!-- old url https://web.archive.org/web/20170828172141/https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html -->| archive-date=December 28, 2022 |access-date=December 28, 2022 |quote=Offenbar hat der PPro einen ladbaren Microcode, für den das Board-BIOS zwei Funktionen im Interrupt 15h zum Auslesen und Laden bereithält (näheres im nächsten Update der Interrupt-Liste). Gedacht ist das für Patches, doch wer weiß, welch ungeahnte Möglichkeiten noch darinstecken. Somit hat man es beim PPro in Zukunft nicht nur mit zwei Masken-Versionen (für CPU und Cache), sondern auch noch mit der Update-Version des Microcode-BIOS zu tun (zum Beispiel beim aktuellen 200-MHz-'P6S' mit der Kennung SY013: CPU-Step A0, Cache-Step B1, BIOS: sA0C05). |trans-quote=Apparently the PPro has a loadable microcode, for which the board BIOS provides two functions in interrupt 15h for reading and loading (more information in the next update of the interrupt list). This is intended for patches, but who knows what undreamt-of possibilities are still there. In the future, therefore, the PPro will not only have to deal with two mask versions (for CPU and cache), but also with the update version of the microcode BIOS (e.g. with the current 200 MHz 'P6S' with the Identifier SY013: CPU step A0, cache step B1, BIOS: sA0C05). |df=dmy-all }}</ref>

<ref name="Stokes_20060405">{{cite news |last1=Stokes |first1=Jon |date=April 5, 2006 |title=Into the Core: Intel's next-generation microarchitecture |url=https://arstechnica.com/gadgets/2006/04/core/ |url-status=live |department=Tech |work=[[Ars Technica]] |language=en-us |oclc=52157687 |archive-url=https://web.archive.org/web/20221218114751/https://arstechnica.com/gadgets/2006/04/core/ |archive-date=December 18, 2022 |access-date=December 28, 2022 |quote=The P6 lineage from the Pentium Pro to the Pentium M [...] One of the most distinctive features of the P6 line is its issue port structure. (Intel calls these "dispatch ports," but for the sake of consistency with the rest of my work I'll be using the terms "dispatch" and "issue" differently than Intel.) Core uses a similar structure in its execution core, although there are some major differences between Core's issue port and RS combination and that of the P6. |df=dmy-all }}</ref>

<ref name="MPR 1995-11-13">{{cite magazine |last1=Slater |first1=Michael |date=November 13, 1995 |title=Intel Boosts Pentium Pro to 200 MHz |url=https://www.ardent-tool.com/CPU/docs/MPR/091501.pdf |magazine=[[Microprocessor Report]] |volume=9 |number=15 |series=MicroDesign Resources |archive-url=https://web.archive.org/web/20211202223030/https://www.ardent-tool.com/CPU/docs/MPR/091501.pdf |access-date=December 28, 2022 |archive-date=December 2, 2021 |url-status=live |quote=Integer Leads, FP Lags RISC Chips |via=Ardent Tool of Capitalism (ardent-tool.com) |df=dmy-all }}</ref>

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