Editing Memory management unit (section)

=== x86 ===
The [[x86]] architecture has evolved over a very long time while maintaining full software compatibility, even for OS code. Thus, the MMU is extremely complex, with many different possible operating modes.

The [[8086]]/[[8088]] and [[80186]]/80188 have no memory management unit; they support segmentation, but only to support more physical memory than a 16-bit address can support, as the segment number, in a segment register, is multiplied by 16 and added to the segment offset to generate a physical address.

The [[80286]] added an MMU that supports segmentation, but not paging. When segmentation is enabled by turning on [[protected mode]], the segment number acts as an index into a table of [[segment descriptor]]s; a segment descriptor contains a base physical address, a segment length, a presence bit to indicate whether the segment is currently in memory, permission bits, and control bits, If the offset in the segment is within the bounds specified by the segment descriptor, that offset is added to the base physical address to generate a physical address.

The [[80386]], which introduced the 32-bit [[IA-32]] version of x86, and subsequent x86 CPUs, support segmentation and paging. If paging is enabled, the base address in a segment descriptor is an address in a linear paged address space divided into {{nowrap|4 KB}} pages, so when that is added to the offset in the segment, the resulting address is a linear address in that address space; in IA-32, that address is then masked to be no larger than 32 bits.  The result may be looked up via a tree-structured page table, with the bits of the address being split as follows: 10 bits for the branch of the tree, 10 bits for the leaves of the branch, and the 12 lowest bits being directly copied to the result. 

Segment registers, used in pre-80386 CPUs to extend the address space, are not used in modern OSes, with one major exception: access to [[thread (computer science)|thread]]-specific data for applications or CPU-specific data for OS kernels, which is done with explicit use of the FS and GS segment registers. All memory access involves a segment register, chosen according to the code being executed. Except when using FS or GS, the OS ensures that the offset will be zero. Some operating systems, such as [[OpenBSD]] with its [[W^X]] feature, and Linux with the [[Exec Shield]] or [[PaX]] patches, may also limit the length of the code segment, as specified by the CS register, to disallow execution of code in modifiable regions of the address space.

Minor revisions of the MMU introduced with the [[Intel P5|Pentium]] have allowed very large {{nowrap|4 MB}} pages by skipping the bottom level of the tree (this leaves 10 bits for indexing the first level of page hierarchy with the remaining 10+12 bits being directly copied to the result).  Minor revisions of the MMU introduced with the [[Pentium Pro]] introduced the [[physical address extension]] (PAE) feature, enabling 36-bit physical addresses with 2+9+9 bits for three-level page tables and 12 lowest bits being directly copied to the result.  Large pages ({{nowrap|2 MB}}) are also available by skipping the bottom level of the tree (resulting in 2+9 bits for two-level table hierarchy and the remaining 9+12 lowest bits copied directly). In addition, the [[page attribute table]] allowed specification of cacheability by looking up a few high bits in a small on-CPU table.

[[Executable-space protection|No-execute]] support was originally only provided on a per-segment basis, making it very awkward to use.
More recent x86 chips provide a per-page [[NX bit]] (no-execute bit) in the PAE mode.
The [[W^X]], [[Exec Shield]], and [[PaX]] mechanisms described above emulate per-page non-execute support on machines with x86 processors that lack the NX bit by setting the length of the code segment, with a performance loss and a reduction in the available address space.

[[File:HSA-enabled virtual memory with distinct graphics card.svg|thumb|right|upright=1.8|[[Heterogeneous System Architecture]] (HSA) creates a unified virtual address space for CPUs, GPUs and DSPs, obsoleting the mapping tricks and data copying.]]

[[x86-64]], the 64-bit version of the x86 architecture, almost entirely removes segmentation in favor of the [[flat memory model]] used by almost all operating systems for the 386 or newer processors.  In long mode, all segment offsets are ignored, except for the FS and GS segments; linear addresses are 64-bit rather than 32-bit, with the lowest 48 bits of the address being significant.  When used with {{nowrap|4 KB}} pages, the page table tree has four levels instead of three, to handle the larger linear addresses; in some newer x86-64 processors, a [[Intel 5-level paging|fifth page table level]] can be enabled, to support 57-bit linear addresses.  In all levels of the page table, the page table entry includes an NX bit.

48-bit linear addresses are divided as follows: 16 bits unused, nine bits each for four tree levels (for a total of 36 bits), and the 12 lowest bits directly copied to the result.  With {{nowrap|2 MB}} pages, there are only three levels of page table, for a total of 27 bits used in paging and 21 bits of offset.  Some newer CPUs also support a {{nowrap|1 GB}} page with two levels of paging and {{nowrap|30 bits}} of offset.<ref name=amd-volume2>{{cite web
| url = http://support.amd.com/TechDocs/24593.pdf
| title = AMD64 Architecture Programmer's Manual Volume 2: System Programming
| date = March 2017
| access-date = 2017-12-05
}}</ref> [[CPUID]] can be used to determine if {{nowrap|1 GB}} pages are supported.

In all three cases, the {{nowrap|16 highest}} bits are required to be equal to the 48th bit, or in other words, the low {{nowrap|48 bits}} are [[sign extension|sign extended]] to the higher bits. This is done to allow further expansion of the addressable range, without compromising backwards compatibility.

57-bit linear addresses are divided as follows: 7 bits unused, nine bits each for five tree levels (for a total of 45 bits), and the 12 lowest bits directly copied to the result. The low {{nowrap|57 bits}} are sign extended.