Editing Transmeta (section)

===VLIW core===
In conjunction with its code-morphing software the Efficeon most closely mirrors the feature set of [[Intel]] [[Pentium 4]] processors, although, like [[AMD]] [[Opteron]] processors, it supports a fully integrated [[memory controller]], a [[HyperTransport]] IO bus, and the [[NX bit]], or no-execute [[x86]] extension to [[Physical Address Extension|PAE mode]]. [[NX bit]] support is available starting with CMS version 6.0.4.

Efficeon's computational performance relative to mobile CPUs like the [[Intel]] [[Pentium M]] is thought to be lower, although little appears to be published about the relative performance of these competing processors.

Efficeon came in two package types: a 783- and a 592-contact [[ball grid array]]. Its power consumption was moderate (with some consuming as little as 3 watts at 1&nbsp;GHz and 7 watts at 1.5&nbsp;GHz), so it could be passively cooled.

Two generations of this chip were produced. The first generation (TM8600) was manufactured using a [[TSMC]] 130&nbsp;nm process and produced at speeds up to 1.1 [[GHz]]. The second generation (TM8800 and TM8820) was manufactured using a Fujitsu 90&nbsp;nm process and produced at speeds ranging from 1&nbsp;GHz to 1.7&nbsp;GHz.

Internally, the Efficeon had two [[arithmetic logic unit]]s, two load/store/add units, two execute units, two [[floating-point]]/[[MMX (instruction set)|MMX]]/[[Streaming SIMD Extensions|SSE]]/[[SSE2]] units, one [[branch predictor|branch prediction unit]], one alias unit, and one control unit. The VLIW core could execute a 256-bit VLIW instruction per cycle. A VLIW is called a molecule and has room to store eight 32-bit instructions (called atoms) per cycle.

The Efficeon had a 128-KB L1 instruction cache, a 64-KB L1 data cache and a 1-MB L2 cache. All caches were on die.

Additionally, Efficeon code morphing software (CMS) reserved a small portion of main memory (typically 32 MB) for its cache of dynamically translated x86 instructions.