Editing System on a chip (section)

==== Network on a chip ====
{{Main|Network on a chip}}
In the late 2010s, a trend of SoCs implementing [[communications subsystem]]s in terms of a network-like topology instead of [[bus (computing)|bus-based]] protocols has emerged. A trend towards more processor cores on SoCs has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.<ref name=":0" />{{Rp|xiii}} This has led to the emergence of interconnection networks with [[Router (computing)|router]]-based [[packet switching]] known as "[[network on a chip|networks on chip]]" (NoCs) to overcome the [[Bottleneck (engineering)|bottlenecks]] of bus-based networks.<ref name=":0" />{{Rp|xiii}}

Networks-on-chip have advantages including destination- and application-specific [[routing]], greater power efficiency and reduced possibility of [[bus contention]]. Network-on-chip architectures take inspiration from [[communication protocols]] like [[Transmission Control Protocol|TCP]] and the [[Internet protocol suite]] for on-chip communication,<ref name=":0" /> although they typically have fewer [[network layer]]s. Optimal network-on-chip [[network architecture]]s are an ongoing area of much research interest. NoC architectures range from traditional distributed computing [[Network topology|network topologies]] such as [[Torus interconnect|torus]], [[Hypercube internetwork topology|hypercube]], [[Mesh networking|meshes]] and [[tree network]]s to [[genetic algorithm scheduling]] to [[randomized algorithm]]s such as [[Branching random walk|random walks with branching]] and randomized [[time to live]] (TTL).

Many SoC researchers consider NoC architectures to be the future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limited [[Floorplan (microelectronics)|floorplanning]] choices as the number of cores in SoCs increase, so as [[three-dimensional integrated circuit]]s (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs.<ref name=":0" />