Editing Synchronous dynamic random-access memory (section)

== {{Anchor|PREFETCH}} DDR SDRAM prefetch architecture==
DDR SDRAM employs prefetch architecture to allow quick and easy access to multiple [[data word]]s located on a common physical row in the memory.

The prefetch architecture takes advantage of the specific characteristics of memory accesses to DRAM. Typical DRAM memory operations involve three phases: [[bitline]] precharge, row access, column access. Row access is the heart of a read operation, as it involves the careful sensing of the tiny signals in DRAM memory cells; it is the slowest phase of memory operation. However, once a row is read, subsequent column accesses to that same row can be very quick, as the sense amplifiers also act as latches. For reference, a row of a 1 [[Gigabit|Gbit]]{{binpre}} [[DDR3]] device is 2,048 [[bit]]s wide, so internally 2,048 bits are read into 2,048 separate sense amplifiers during the row access phase. Row accesses might take 50 [[nanosecond|ns]], depending on the speed of the DRAM, whereas column accesses off an open row are less than 10 ns.

Traditional DRAM architectures have long supported fast column access to bits on an open row. For an 8-bit-wide memory chip with a 2,048 bit wide row, accesses to any of the 256 datawords (2048/8) on the row can be very quick, provided no intervening accesses to other rows occur.

The drawback of the older fast column access method was that a new column address had to be sent for each additional dataword on the row. The address bus had to operate at the same frequency as the data bus. Prefetch architecture simplifies this process by allowing a single address request to result in multiple data words.

In a prefetch buffer architecture, when a memory access occurs to a row the buffer grabs a set of adjacent data words on the row and reads them out ("bursts" them) in rapid-fire sequence on the IO pins, without the need for individual column address requests. This assumes the CPU wants adjacent datawords in memory, which in practice is very often the case. For instance, in DDR1, two adjacent data words will be read from each chip in the same clock cycle and placed in the pre-fetch buffer. Each word will then be transmitted on consecutive rising and falling edges of the clock cycle. Similarly, in DDR2 with a 4n pre-fetch buffer, four consecutive data words are read and placed in buffer while a clock, which is twice faster than the internal clock of DDR, transmits each of the word in consecutive rising and falling edge of the faster external clock <ref>Micron, General DDR SDRAM Functionality, Technical Note, TN-46-05</ref>

The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency. In an 8n prefetch architecture (such as [[DDR3]]), the IOs will operate 8 times faster than the memory core (each memory access results in a burst of 8 datawords on the IOs). Thus, a 200&nbsp;MHz memory core is combined with IOs that each operate eight times faster (1600 megabits per second). If the memory has 16 IOs, the total read bandwidth would be 200&nbsp;MHz x 8 datawords/access x 16 IOs = 25.6 gigabits per second (Gbit/s) or 3.2 gigabytes per second (GB/s). Modules with multiple DRAM chips can provide correspondingly higher bandwidth.

Each generation of SDRAM has a different prefetch buffer size:

* [[DDR SDRAM]]'s prefetch buffer size is 2n (two datawords per memory access)
* [[DDR2 SDRAM]]'s prefetch buffer size is 4n (four datawords per memory access)
* [[DDR3 SDRAM]]'s prefetch buffer size is 8n (eight datawords per memory access)
* [[DDR4 SDRAM]]'s prefetch buffer size is 8n (eight datawords per memory access)
* [[DDR5 SDRAM]]'s prefetch buffer size is 8n; there is an additional mode of 16n