Editing Semiconductor device fabrication (section)

==Device test==
{{Main|Wafer testing}}

Once the front-end process has been completed, the semiconductor devices or chips are subjected to a variety of electrical tests to determine if they function properly. The percent of devices on the wafer found to perform properly is referred to as the '''yield'''. Manufacturers are typically secretive about their yields,<ref name="ceicm-chapter-3">{{Cite book |title=Cost Effective Integrated Circuit Manufacturing |url=https://smithsonianchips.si.edu/ice/cd/CEICM/SECTION3.pdf |chapter=Yield and Yield Management |chapter-url=https://smithsonianchips.si.edu/ice/cd/CEICM/SECTION3.pdf |publisher=Integrated Circuit Engineering Corporation |isbn=1-877750-60-3 |date=1997 |access-date=2023-01-22 |archive-url=https://web.archive.org/web/20230122020617/https://smithsonianchips.si.edu/ice/cd/CEICM/SECTION3.pdf |archive-date=2023-01-22 |url-status=bot: unknown }}</ref> but it can be as low as 30%, meaning that only 30% of the chips on the wafer work as intended. [[Process variation (semiconductor)|Process variation]] is one among many reasons for low yield. Testing is carried out to prevent faulty chips from being assembled into relatively expensive packages.

The yield is often but not necessarily related to device (die or chip) size. As an example, in December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their [[5nm]] test chips with a [[Die (integrated circuit)|die]] size of 17.92&nbsp;mm<sup>2</sup>. The yield went down to 32% with an increase in die size to 100&nbsp;mm<sup>2</sup>.<ref>{{Cite web|url=https://www.anandtech.com/show/15219/early-tsmc-5nm-test-chip-yields-80-hvm-coming-in-h1-2020|title=Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020|first=Dr Ian|last=Cutress|website=[[AnandTech]]|access-date=2020-04-12|archive-date=2020-05-25|archive-url=https://web.archive.org/web/20200525115643/https://www.anandtech.com/show/15219/early-tsmc-5nm-test-chip-yields-80-hvm-coming-in-h1-2020|url-status=live}}</ref> The number of killer defects on a wafer, regardless of die size, can be noted as the defect density (or D<sub>0</sub>) of the wafer per unit area, usually cm<sup>2</sup>.

The fab [[Wafer testing|tests the chips on the wafer]] with an electronic tester that presses tiny probes against the chip.  The machine marks each bad chip with a drop of dye.  Currently, electronic dye marking is possible if wafer test data (results) are logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to predetermined test limits such as maximum operating frequencies/clocks, number of working (fully functional) cores per chip, etc. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging. Binning allows chips that would otherwise be rejected to be reused in lower-tier products, as is the case with GPUs and CPUs, increasing device yield, especially since very few chips are fully functional (have all cores functioning correctly, for example). [[eFUSE]]s may be used to disconnect parts of chips such as cores, either because they did not work as intended during binning, or as part of market segmentation (using the same chip for low, mid and high-end tiers). Chips may have spare parts to allow the chip to fully pass testing even if it has several non-working parts.

Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package.  This is referred to as the "final test". Chips may also be imaged using x-rays.

Usually, the fab charges for testing time, with prices on the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible because many testers have the resources to perform most or all of the tests in parallel and on several chips at once.

Chips are often designed with "testability features" such as [[scan chain]]s or a "[[built-in self-test]]" to speed testing and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly distributed resistance values as specified by the design.

Good designs try to test and statistically manage ''[[process corners|corners]]'' (extremes of silicon behavior caused by a high [[operating temperature]] combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.