Editing PDP-10 (section)

=== Instructions ===
{| class="infobox" style="font-size:88%;width:36em;"
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|+ DEC PDP-10 instruction formats
|-
|
{| style="font-size:88%;"
|- 
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:60px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>3</sup><sub>5</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- 
|colspan="20" | '''General instructions'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="9"| <div style="display:inline-block; width:12px">&nbsp;</div> Opcode
| style="text-align:center" colspan="4"| <div style="display:inline-block; width:6px">&nbsp;</div> Acc #
| style="text-align:center" colspan="1"| <div style="display:inline-block; width:0px">&nbsp;</div> I
| style="text-align:center" colspan="4"| <div style="display:inline-block; width:0px">&nbsp;</div> Index #
| style="text-align:center" colspan="17"| <div style="display:inline-block; width:12px">&nbsp;</div> Memory address
|- 
|colspan="12" | '''I/O instructions'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="3"| <div style="display:inline-block; width:8px">&nbsp;</div> 7
| style="text-align:center" colspan="7"| <div style="display:inline-block; width:12px">&nbsp;</div> Device #
| style="text-align:center" colspan="3"| Opcode
| style="text-align:center" colspan="1"| <div style="display:inline-block; width:0px">&nbsp;</div> I
| style="text-align:center" colspan="4"| <div style="display:inline-block; width:0px">&nbsp;</div> Index #
| style="text-align:center" colspan="17"| <div style="display:inline-block; width:12px">&nbsp;</div> Memory address
|} 
|}
Instructions are stored in 36-bit words. There are two formats, general instructions and [[input/output]] instructions.{{sfn|Programming|1970|p=13}}

In general instructions, the leftmost 9 bits, 0 to 8, contain an instruction [[opcode]]. Many of the possible 512 codes are not defined in the base model machines and are reserved for expansion like the addition of a hardware [[floating point unit]]. Following the opcode in bits 9 to 12 is the number of a register which will be used for the instruction. The input/output instructions all start with bits 0 through 2 being set to 1 (decimal value 7), bits 3 through 9 containing a device number, and 10 through 12 the instruction opcode.{{sfn|Programming|1970|p=13}}

In both formats, bits 13 through 35 are used to form the "effective address", E. Bits 18 through 35 contain a numerical constant address, Y. This address may be modified by adding the 18-bit value in a register, X, the register number indicated in bits 14 to 17. If these are set to zero, no indexing is used, meaning register 0 cannot be used for indexing. Bit 13, I, indicates indirection, meaning the ultimate effective address used by the instruction is not E, but the address stored in memory location E. When using indirection, the data in word E is interpreted in the same way as the layout of the instruction; bits 0 to 12 are ignored, and 13 through 35 form I, X and Y as above.

Instruction execution begins by calculating E. It adds the contents of the given register X (if not 0) to the offset Y; then, if the indirect bit is 1, the value at E is fetched and the effective address calculation is repeated. If I is 1 in the stored value at E in memory, the system will then indirect through that address as well, possibly following many such steps.{{sfn|Programming|1970|p=13}} This process continues until an indirect word with a zero indirect bit is reached. Indirection of this sort was a common feature of processor designs of this era.

In supervisor mode, addresses correspond directly to physical memory. In user mode, addresses are translated to physical memory. Earlier models give a user process a "high" and a "low" memory: addresses with a 0 top bit use one base register and those with a 1 use another. Each segment is contiguous.  Later architectures have paged memory access, allowing non-contiguous address spaces. The CPU's general-purpose registers can also be addressed as memory locations 0–15.

====General instructions====
There are three main classes of general instructions: arithmetic, logical, and move; conditional jump; conditional skip (which may have side effects). There are also several smaller classes.

The arithmetic, logical, and move operations include variants which operate immediate-to-register, memory-to-register, register-to-memory, register-and-memory-to-both or memory-to-memory. Since registers may be addressed as part of memory, register-to-register operations are also defined. (Not all variants are useful, though they are well-defined.) For example, the ADD operation has as variants ADDI (add an 18-bit ''I''mmediate constant to a register), ADDM (add register contents to a ''M''emory location), ADDB (add to ''B''oth, that is, add register contents to memory and also put the result in the register). A more elaborate example is HLROM (''H''alf ''L''eft to ''R''ight, ''O''nes to ''M''emory), which takes the Left half of the register contents, places them in the Right half of the memory location, and replaces the left half of the memory location with Ones. Halfword instructions are also used for linked lists: HLRZ is the Lisp CAR operator; HRRZ is CDR.

The conditional jump operations examine register contents and jump to a given location depending on the result of the comparison. The mnemonics for these instructions all start with JUMP, JUMPA meaning "jump always" and JUMP meaning "jump never" – as a consequence of the symmetric design of the instruction set, it contains several no-ops such as JUMP. For example, JUMPN A,LOC jumps to the address LOC if the contents of register A is non-zero. There are also conditional jumps based on the processor's condition register using the JRST instruction. On the KA10 and KI10, JRST is faster than JUMPA, so the standard unconditional jump is JRST.

The conditional skip operations compare register and memory contents and skip the next instruction (which is often an unconditional jump) depending on the result of the comparison. A simple example is CAMN A,LOC which compares the contents of register A with the contents of location LOC and skips the next instruction if they are not equal.  A more elaborate example is TLCE A,LOC (read "Test Left Complement, skip if Equal"), which using the contents of LOC as a mask, selects the corresponding bits in the left half of register A. If all those bits are ''E''qual to zero, skip the next instruction; and in any case, replace those bits by their Boolean complement.

Some smaller instruction classes include the shift/rotate instructions and the procedure call instructions. Particularly notable are the stack instructions PUSH and POP, and the corresponding stack call instructions PUSHJ and POPJ. The byte instructions use a special format of indirect word to extract and store arbitrary-sized bit fields, possibly advancing a pointer to the next unit.{{efn|cf. {{section link|Byte addressing|Hybrid systems}}}}

====Input/output instructions====
The PDP-10 does not use [[Memory-mapped I/O and port-mapped I/O|memory-mapped devices]], in contrast to the [[PDP-11]] and later DEC machines. A separate set of instructions is used to move data to and from devices defined by a device number in the instruction. Bits 3 to 9 contain the device number, with the 7 bits allowing a total of 128 devices. Instructions allow for the movement of data to and from devices in word-at-a-time (DATAO and DATAI) or block-at-a-time (BLKO, BLKI).{{sfn|Programming|1970|pp=87-88}}

In block mode, the value pointed to by E is a word in memory that is split in two, the right 18 bits indicate a starting address in memory where the data is located (or written into) and the left 18 bits are a counter. The block instructions increment both values every time they are called, thereby increasing the counter as well as moving to the next location in memory. It then performs a DATAO or DATAI. Finally, it checks the counter side of the value at E, if it is non-zero, it skips the next instruction. If it is zero, it performs the next instruction, normally a JUMP back to the top of the loop.{{sfn|Programming|1970|p=88}} The BLK instructions are effectively small programs that loop over a DATA and increment instructions, but by having this implemented in the processor itself, it avoids the need to repeatedly read the series of instructions from main memory and thus performs the loop much more rapidly.{{sfn|Programming|1970|p=89}}

The final set of I/O instructions are used to write and read condition codes on the device, CONO and CONI.{{sfn|Programming|1970|p=86}} Additionally, CONSZ will perform a CONI, bitmask the retrieved data against the value in E, and then skip the next instruction if it is zero, used in a fashion similar to the BLK commands. Only the right 18 bits are tested in CONSZ.{{sfn|Programming|1970|p=87}}