Editing Memory management unit (section)

=== PowerPC ===
{{Unreferenced section|date=June 2023}}
In [[PowerPC]] G1, G2, G3, and G4 pages are normally {{nowrap|4 KB.}}  After a TLB miss, the standard PowerPC MMU begins two simultaneous lookups.  One lookup attempts to match the address with one of four or eight data block address translation (DBAT) registers, or four or eight instruction block address translation registers (IBAT), as appropriate.  The BAT registers can map linear chunks of memory as large as {{nowrap|256 MB,}} and are normally used by an OS to map large portions of the address space for the OS kernel's own use.  If the BAT lookup succeeds, the other lookup is halted and ignored.

The other lookup, not directly supported by all processors in this family, is via a so-called [[inverted page table]], which acts as a hashed off-chip extension of the TLB. First, the top four bits of the address are used to select one of 16 [[memory segmentation|segment]] registers. Then 24 bits from the segment register replace those four bits, producing a 52-bit address.  The use of segment registers allows multiple processes to share the same [[hash table]].

The 52-bit address is hashed, then used as an index into the off-chip table. There, a group of eight-page table entries is scanned for one that matches. If none match due to excessive [[hash collision]]s, the processor tries again with a slightly different [[hash function]]. If this, too, fails, the CPU traps into OS (with MMU disabled) so that the problem may be resolved. The OS needs to discard an entry from the hash table to make space for a new entry.  The OS may generate the new entry from a more normal tree-like page table or from per-mapping data structures which are likely to be slower and more space-efficient.  Support for [[NX bit|no-execute]] control is in the segment registers, leading to {{nowrap|256 MB}} granularity.

A major problem with this design is poor [[cache locality]] caused by the hash function.  Tree-based designs avoid this by placing the page table entries for adjacent pages in adjacent locations.  An operating system running on the PowerPC may minimize the size of the hash table to reduce this problem.

It is also somewhat slow to remove the page table entries of a process.  The OS may avoid reusing segment values to delay facing this, or it may elect to suffer the waste of memory associated with per-process hash tables.  G1 chips do not search for page table entries, but they do generate the hash, with the expectation that an OS will search the standard hash table via software.  The OS can write to the TLB.  G2, G3, and early G4 chips use hardware to search the hash table.  The latest chips allow the OS to choose either method.  On chips that make this optional or do not support it at all, the OS may choose to use a tree-based page table exclusively.