Editing MIPS architecture (section)

=== MIPS MCU ===
Enhancements for microcontroller applications. The MCU ASE (application-specific extension) has been developed to extend the [[interrupt]] controller support, reduce the interrupt latency and enhance the I/O peripheral control function typically required in microcontroller system designs.
* Separate priority and vector generation
* Supports up to 256 interrupts in EIC (External Interrupt Controller) mode and eight hardware interrupt pins
* Provides 16-bit vector offset address
* Pre-fetching of the interrupt exception vector
* Automated Interrupt Prologue – adds hardware to save and update system status before the interrupt handling routine
* Automated Interrupt Epilogue – restores the system state previously stored in the stack for returning from the interrupt.
* Interrupt Chaining – supports the service of pending interrupts without the need to exit the initial interrupt routine, saving the cycles required to store and restore multiple active interrupts
* Supports speculative pre-fetching of the interrupt vector address. Reduces the number of interrupt service cycles by overlapping memory accesses with pipeline flushes and exception prioritization
* Includes atomic bit set/clear instructions which enables bits within an I/O register that are normally used to monitor or control external peripheral functions to be modified without interruption, ensuring the action is performed securely.