Editing Intel 8080 (section)

===Pin use===
[[File:Intel 8080 Microprocessor.png|thumb|300px|8080 [[pinout]]]]

The address bus has its own 16 pins, and the data bus has 8 pins that are usable without any multiplexing. Using the two additional pins (read and write signals), it is possible to assemble simple microprocessor devices very easily. Only the separate IO space, interrupts, and DMA need added chips to decode the processor pin signals. However, the pin load capacity is limited; even simple computers often require bus amplifiers.

The processor needs three power sources (−5, +5, and +12&nbsp;V) and two non-overlapping high-amplitude synchronizing signals. However, at least the late Soviet version КР580ВМ80А was able to work with a single +5&nbsp;V power source, the +12&nbsp;V pin being connected to +5&nbsp;V and the −5&nbsp;V pin to ground.

The pin-out table, from the chip's accompanying documentation, describes the pins as follows:

{| class="wikitable"
 ! Pin number
 ! Signal
 ! Type
 ! Comment
 |-
 | 1 || A10
 | Output || Address bus 10
 |-
 | 2 || GND
 | — || Ground
 |-
 | 3 || D4
 | rowspan="8" | Bidirectional
 | rowspan="8" | Bidirectional data bus. The processor also transiently sets here the "processor state", providing information about what the processor is currently doing:
*D0 reading interrupt command. In response to the interrupt signal, the processor is reading and executing a single arbitrary command with this flag raised. Normally the supporting chips provide the subroutine call command (CALL or RST), transferring control to the interrupt handling code.
*D1 reading (low level means writing)
*D2 accessing stack (probably a separate stack memory space was initially planned)
*D3 doing nothing, has been halted by the [[HLT (x86 instruction)|HLT]] instruction
*D4 writing data to an output port
*D5 reading the first byte of an executable instruction
*D6 reading data from an input port
*D7 reading data from memory
 |-
 | 4 || D5
 |-
 | 5 || D6
 |-
 | 6 || D7
 |-
 | 7 || D3
 |-
 | 8 || D2
 |-
 | 9 || D1
 |-
 | 10 || D0
 |-
 | 11 || −5 V
 | — || The −5 V power supply. This must be the first power source connected and the last disconnected, otherwise the processor will be damaged.
 |-
 | 12 || RESET
 | Input || Reset. This active low signal forces execution of commands located at address 0000. The content of other processor registers is not modified.
 |-
 | 13 || HOLD
 | Input || Direct memory access request. The processor is requested to switch the data and address bus to the high impedance ("disconnected") state.
 |-
 | 14 || INT
 | Input || Interrupt request
 |-
 | 15 || φ2
 | Input || The second phase of the clock generator signal
 |-
 | 16 || INTE
 | Output || The processor has two commands for setting 0 or 1 level on this pin. The pin normally is supposed to be used for interrupt control. However, in simple computers it was sometimes used as a single bit output port for various purposes.
 |-
 | 17 || DBIN
 | Output || Read (the processor reads from memory or input port)
 |-
 | 18 || WR
 | Output || Write (the processor writes to memory or output port). This is an active low output.
 |-
 | 19 || SYNC
 | Output || Active level indicates that the processor has put the "state word" on the data bus. The various bits of this state word provide added information to support the separate address and memory spaces, interrupts, and direct memory access. This signal is required to pass through additional logic before it can be used to write the processor state word from the data bus into some external register, e.g., [http://www.datasheets360.com/pdf/-4828066515233335508 8238] {{Webarchive|url=https://web.archive.org/web/20230918030959/https://www.datasheets360.com/pdf/-4828066515233335508 |date=September 18, 2023 }}-System Controller and Bus Driver.
 |-
 | 20 || +5 V || — || The + 5&nbsp;V power supply
 |-
 | 21 || HLDA
 | Output || Direct memory access confirmation. The processor switches data and address pins into the high impedance state, allowing another device to manipulate the bus
 |-
 | 22 || φ1
 | Input || The first phase of the clock generator signal
 |-
 | 23 || READY
 | Input || Wait. With this signal it is possible to suspend the processor's work. It is also used to support the hardware-based step-by step debugging mode.
 |-
 | 24 || WAIT
 | Output || Wait (indicates that the processor is in the waiting state)
 |-
 | 25 || A0
 | rowspan="3" | Output
 | rowspan="3" | Address bus
 |-
 | 26 || A1
 |-
 | 27 || A2
 |-
 | 28 || 12 V
 | — || The +12 V power supply. This must be the ''last'' connected and first disconnected power source.
 |-
 | 29 || A3
 | rowspan="12" | Output
 | rowspan="12" | The address bus; can switch into high impedance state on demand
 |-
 | 30 || A4
 |-
 | 31 || A5
 |-
 | 32 || A6
 |-
 | 33 || A7
 |-
 | 34 || A8
 |-
 | 35 || A9
 |-
 | 36 || A15
 |-
 | 37 || A12
 |-
 | 38 || A13
 |-
 | 39 || A14
 |-
 | 40 || A11
 |}