Editing HyperTransport (section)

== Infinity Fabric ==
'''Infinity Fabric''' ('''IF''') is a superset of HyperTransport announced by AMD in 2016 as an interconnect for its GPUs and CPUs. It is also usable as interchip interconnect for communication between CPUs and GPUs (for [[Heterogeneous System Architecture]]), an arrangement known as '''Infinity Architecture'''.<ref>{{cite web |author=AMD |title=AMD_presentation_EPYC |url=https://s14.postimg.org/rgf0wv38x/image.jpg |access-date=May 24, 2017 |ref=AMD_presentation_EPYC |archive-url=https://web.archive.org/web/20170821125859/https://s14.postimg.org/rgf0wv38x/image.jpg |archive-date=August 21, 2017 |url-status=dead}}</ref><ref>{{cite web |last1=Merritt |first1=Rick |date=December 13, 2016 |title=AMD Clocks Ryzen at 3.4 GHz+ |url=http://www.eetimes.com/document.asp?doc_id=1330981&page_number=2 |website=EE Times |language=en-US |access-date=January 17, 2017 |url-status=dead |archive-url=https://web.archive.org/web/20190808171653/https://www.eetimes.com/document.asp?doc_id=1330981&page_number=2 |archive-date=August 8, 2019}}</ref><ref>{{cite web |last1=Alcorn |first1=Paul |date=March 5, 2020 |title=AMD's CPU-to-GPU Infinity Fabric Detailed |url=https://www.tomshardware.com/news/amd-infinity-fabric-cpu-to-gpu |website=Tom's Hardware |language=en-US |access-date=November 12, 2022}}</ref> The company said the Infinity Fabric would scale from 30{{nbsp}}GB/s to 512{{nbsp}}GB/s, and be used in the [[Zen (microarchitecture)|Zen]]-based CPUs and [[Graphics Core Next#Graphics Core Next 5|Vega]] GPUs which were subsequently released in 2017.

On Zen and [[Zen+]] CPUs, the "SDF" data interconnects are run at the same frequency as the DRAM memory clock (MEMCLK), a decision made to remove the latency caused by different clock speeds. As a result, using a faster RAM module makes the entire bus faster.  The links are 32-bit wide, as in HT, but 8 transfers are done per cycle (128-bit packets) compared to the original 2. Electrical changes are made for higher power efficiency.<ref>{{cite web |title=Infinity Fabric (IF) - AMD |url=https://en.wikichip.org/wiki/amd/infinity_fabric |website=WikiChip |language=en-US}}</ref> On [[Zen 2]] and [[Zen 3]] CPUs, the IF bus is on a separate clock, either in a 1:1 or a 2:1 ratio to the DRAM clock. This avoids a limitation on desktop platforms where maximum DRAM speeds were in practice limited by the IF speed. The bus width has also been doubled.<ref>{{Cite web |last=Cutress |first=Ian |date=June 10, 2019 |title=AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome |url=https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/11 |website=AnandTech |language=en-US |access-date=November 12, 2022}}</ref> On [[Zen 4]] and later CPUs, the IF bus is able to run at an asynchronous clock to the DRAM, to allow the higher clock speeds that DDR5 is capable of.<ref>{{cite web |last1=Killian |first1=Zak |title=AMD Addresses Zen 4 Ryzen 7000 Series Memory Overclocking And Configuration Details |url=https://hothardware.com/news/amd-addresses-zen-4-memory-oc-details |website=HotHardware |access-date=4 April 2024 |language=en-us |date=1 September 2022}}</ref>

[[UALink]] will utilize Infinity Fabric as the primary shared memory protocol.