Editing Central processing unit (section)

===Cache===
A [[CPU cache]]<ref>{{cite web |author=Torres |first=Gabriel |date=September 12, 2007 |title=How The Cache Memory Works |url=https://hardwaresecrets.com/how-the-cache-memory-works/ |access-date=January 29, 2023 |website=Hardware Secrets}}</ref> is a [[hardware cache]] used by the central processing unit (CPU) of a [[computer]] to reduce the average cost (time or energy) to access [[Data (computing)|data]] from the [[main memory]]. A cache is a smaller, faster memory, closer to a [[processor core]], which stores copies of the data from frequently used main [[memory location]]s. Most CPUs have different independent caches, including [[Instruction cache|instruction]] and [[data cache]]s, where the data cache is usually organized as a hierarchy of several cache levels (L1, L2, L3, L4, etc.). Each ascending cache level is typically slower but larger than the preceding level with L1 being the fastest and the closest to the CPU.

All modern (fast) CPUs (with few specialized exceptions{{efn|A few specialized CPUs, accelerators or microcontrollers do not have a cache. To be fast, if needed/wanted, they still have an on-chip scratchpad memory that has a similar function, while software managed. In e.g. microcontrollers it can be better for hard real-time use, to have that or at least no cache, as with one level of memory latencies of loads are predictable.}}) have multiple levels of CPU caches. The first CPUs that used a cache had only one level of cache; unlike later level 1 caches, it was not split into L1d (for data) and L1i (for instructions). Almost all current CPUs with caches have a split L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split and acts as a common repository for the already split L1 cache. Every core of a [[multi-core processor]] has a dedicated L2 cache and is usually not shared between the cores. The L3 cache, and higher-level caches, are shared between the cores and are not split. An L4 cache is currently uncommon, and is generally on [[dynamic random-access memory]] (DRAM), rather than on [[static random-access memory]] (SRAM), on a separate die or chip. That was also the case historically with L1, while bigger chips have allowed integration of it and generally all cache levels, with the possible exception of the last level. Each extra level of cache tends to be bigger and is optimized differently.

Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the [[translation lookaside buffer]] (TLB) that is part of the [[memory management unit]] (MMU) that most CPUs have.

Caches are generally sized in powers of two: 2, 8, 16 etc. [[Kibibyte|KiB]] or [[Mebibyte|MiB]] (for larger non-L1) sizes, although the [[IBM z13 (microprocessor)|IBM z13]] has a 96 KiB L1 instruction cache.<ref>{{cite web|url=http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-date=2022-10-09 |url-status=live|title=IBM z13 and IBM z13s Technical Introduction|page=20|date=March 2016|publisher=[[IBM]]}} {{verify source |date=August 2019 |reason=This ref was deleted ([[Special:Diff/897933560]]) by a bug in VisualEditor and later restored by a bot from the original cite at [[Special:Permalink/895110016]] cite #3 – please verify the cite's accuracy and remove this {verify source} template. [[User:GreenC bot/Job 18]]}}</ref>