Editing Accelerated Graphics Port (section)

===AGP command codes===
Like PCI, each AGP transaction begins with an address phase, communicating an address and 4-bit command code. The possible commands are different from PCI, however:

; 000p: Read
: Read 8×(AD[2:0]+1) = 8, 16, 24, ..., 64 bytes. The least significant bit p is 0 for low-priority, 1 for high.
; 001x: (reserved):
; 010p: Write
: Write 8×(AD[2:0]+1) = 8&ndash;64 bytes.
; 011x: (reserved):
; 100p: Long read
: Read 32×(AD[2:0]+1) = 32, 64, 96, ..., 256 bytes. This is the same as a read request, but the length is multiplied by four.
; 1010: Flush
: Force previously written data to memory, for synchronization. This acts as a low-priority read, taking a queue slot and returning 8 bytes of random data to indicate completion. The address and length supplied with this command are ignored.
; 1011: (reserved):
; 1100: Fence
: This acts as a [[memory fence]], requiring that all earlier AGP requests complete before any following requests. Ordinarily, for increased performance, AGP uses a very weak [[consistency model]], and allows a later write to pass an earlier read. (E.g. after sending "write 1, write 2, read, write 3, write 4" requests, all to the same address, the read may return any value from 2 to 4. Only returning 1 is forbidden, as writes must complete before following reads.) This operation does not require any queue slots.
; 1101: Dual address cycle
: When making a request to an address above 2<sup>32</sup>, this is used to indicate that a second address cycle will follow with additional address bits. This operates like a regular PCI dual address cycle; it is accompanied by the low-order 32 bits of the address (and the length), and the following cycle includes the high 32 address bits and the desired command. The two cycles make one request, and take only one slot in the request queue. This request code is not used with side-band addressing.
; 111x: (reserved):

AGP 3.0 dropped high-priority requests and the long read commands, as they were little used. It also mandated side-band addressing, thus dropping the dual address cycle, leaving only four request types: low-priority read (0000), low-priority write (0100), flush (1010) and fence (1100).