Editing Phase-locked loop (section)

===Jitter and noise reduction===
One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the '''static phase offset''' (also called the '''steady-state phase error'''). The variance between these phases is called '''tracking [[jitter]]'''. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible.{{Dubious|date=September 2010}}<!-- If phase variance between input and output is 0, no jitter attenuation is possible. -->

[[Phase noise]] is another type of jitter observed in PLLs, and is caused by the oscillator itself and by elements used in the oscillator's frequency control circuit. Some technologies are known to perform better than others in this regard. The best digital PLLs are constructed with emitter-coupled logic ([[Emitter coupled logic|ECL]]) elements, at the expense of high power consumption. To keep phase noise low in PLL circuits, it is best to avoid saturating logic families such as transistor-transistor logic ([[transistor-transistor logic|TTL]]) or [[CMOS]].<ref>{{Cite book|last1=Basab Bijoy Purkayastha|title=A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel|last2=Kandarpa Kumar Sarma|publisher=Springer (India) Pvt. Ltd. (Part of Springer Science+Business Media)|year=2015|isbn=978-81-322-2040-4|location=India|pages=5}}</ref>

Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated. This is called substrate and [[Power supply rejection ratio|supply noise rejection]]. The higher the noise rejection, the better.

To further improve the phase noise of the output, an [[injection locked oscillator]] can be employed following the VCO in the PLL.