Editing MOS Technology 6502 (section)

===Instructions and opcodes===
6502 instruction [[opcode|operation code]]s (''opcodes'') are 8&nbsp;bits long and have the general form AAABBBCC, where AAA and CC define the opcode, and BBB defines the addressing mode.<ref name=ii>{{cite web |url=http://nparker.llx.com/a2/opcodes.html |title=The 6502/65C02/65C816 Instruction Set Decoded |first=Neil |last=Parker |website=Neil Parker's Apple II page |access-date=2019-07-16 |archive-date=2019-07-16 |archive-url=https://web.archive.org/web/20190716023057/http://nparker.llx.com/a2/opcodes.html |url-status=live}}</ref> For example, the <code>ORA</code> instruction performs a bitwise OR on the bits in the accumulator with another value. The instruction opcode is of the form 000bbb01, where bbb may be 010 for an immediate mode value (constant), 001 for zero-page fixed address, 011 for an absolute address, and so on.<ref name=ii/> This pattern is not universal, as there are exceptions, but it allows opcode values to be easily converted to assembly mnemonics for the majority of instructions, handling the edge cases with special-purpose code.<ref name=ii/>

Of the 256 possible opcodes available using an 8-bit pattern, the original 6502 uses 151 of them, organized into 56 instructions with (possibly) multiple [[addressing mode]]s. Depending on the instruction and addressing mode, the opcode may require zero, one or two additional bytes for operands. Hence 6502 machine instructions vary in length from one to three bytes.<ref>[http://www.masswerk.at/6502/6502_instruction_set.html 6502 Instruction Set] {{Webarchive|url=https://web.archive.org/web/20180508053805/http://www.masswerk.at/6502/6502_instruction_set.html |date=2018-05-08}}.</ref><ref>[http://www.6502.org/tutorials/6502opcodes.html NMOS 6502 Opcodes]. {{Webarchive|url=https://web.archive.org/web/20160114001557/http://www.6502.org/tutorials/6502opcodes.html |date=2016-01-14}}.</ref> The operand is stored in the 6502's customary [[endianness|little-endian format]].

Each CPU machine instruction takes up a certain number of clock cycles, usually equal to the number of memory accesses. For example, the absolute indexing mode of the ORA instruction takes 4 clock cycles; 3 cycles to read the instruction and 1 cycle to read the value of the absolute address. If no memory is accessed, the number of clock cycles is two. The minimum clock cycles for any instruction is two. When using indexed addressing, if the result crosses a page boundary an extra clock cycle is added. Also, when a zero page address is used in indexing mode (e.g. zp,X) an extra clock cycle is added.

The [[WDC 65C816|65C816]], the 16-bit [[CMOS]] descendant of the 6502, also supports 24-bit addressing, which results in instructions being assembled with three-byte operands, also arranged in little-endian format.

The remaining 105 opcodes are undefined. In the original design, instructions where the low-order 4&nbsp;bits (''nibble'') were 3, 7, B or F were not used, providing room for future expansion. Likewise, the $x2 column had only a single entry, <code>LDX #''constant''</code>. The remaining 25 empty slots were distributed. Some of the empty slots were used in the 65C02 to provide both new instructions and variations on existing ones with new addressing modes. The $xF instructions were initially left free to allow 3rd-party vendors to add their own instructions, but later versions of the 65C02 standardized a set of [[bit manipulation]] instructions developed by [[Rockwell Semiconductor]].