Editing Direct memory access (section)

=== AHB ===
{{main|Advanced Microcontroller Bus Architecture}}

In [[System-on-a-chip|systems-on-a-chip]] and [[embedded system]]s, typical system bus infrastructure is a complex on-chip bus such as [[Advanced Microcontroller Bus Architecture#High-performance Bus|AMBA High-performance Bus]]. AMBA defines two kinds of AHB components: master and slave. A slave interface is similar to programmed I/O through which the software (running on embedded CPU, e.g. [[ARM architecture|ARM]]) can write/read I/O registers or (less commonly) local memory blocks inside the device. A master interface can be used by the device to perform DMA transactions to/from system memory without heavily loading the CPU.

Therefore, high bandwidth devices such as network controllers that need to transfer huge amounts of data to/from system memory will have two interface adapters to the AHB: a master and a slave interface. This is because on-chip buses like AHB do not support [[Three-state logic|tri-stating]] the bus or alternating the direction of any line on the bus. Like PCI, no central DMA controller is required since the DMA is bus-mastering, but an [[Arbiter (electronics)|arbiter]] is required in case of multiple masters present on the system.

Internally, a multichannel DMA engine is usually present in the device to perform multiple concurrent [[scatter-gather]] operations as programmed by the software.