Editing Verilog (section)

==Fork/join==
The '''fork/join''' pair are used by Verilog to create parallel processes. All statements (or blocks) between a fork/join pair begin execution simultaneously upon execution flow hitting the '''fork'''. Execution continues after the '''join''' upon completion of the longest running statement or block between the '''fork''' and '''join'''.
<syntaxhighlight lang="verilog">
initial
  fork
    $write("A"); // Print char A
    $write("B"); // Print char B
    begin
      #1; // Wait 1 time unit
      $write("C"); // Print char C
    end
  join
</syntaxhighlight>

The way the above is written, it is possible to have either the sequences "ABC" or "BAC" print out. The order of simulation between the first $write and the second $write depends on the simulator implementation, and may purposefully be randomized by the simulator. This allows the simulation to contain both accidental race conditions as well as intentional non-deterministic behavior.

Notice that VHDL cannot dynamically spawn multiple processes like Verilog.<ref>{{cite web |first=Clifford E. |last=Cummings |title=SystemVerilog – Is This The Merging of Verilog & VHDL? |year=2003 |publisher=SNUG Boston 2003 |url=http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_SystemVerilog_VHDL.pdf }}</ref>