Editing Static random-access memory (section)

===By function===
* [[Asynchronous circuit|Asynchronous]]{{snd}} independent of clock frequency; data in and data out are controlled by address transition. Examples include the ubiquitous 28-pin 8K&nbsp;×&nbsp;8 and 32K&nbsp;×&nbsp;8 chips (often but not always named something along the lines of [[6264]] and 62C256 respectively), as well as similar products up to 16&nbsp;Mbit per chip.
* [[Synchronous]]{{snd}} all timings are initiated by the clock edges. Address, data in and other control signals are associated with the clock signals.
In the 1990s, asynchronous SRAM used to be employed for fast access time. Asynchronous SRAM was used as [[main memory]] for small cache-less embedded processors used in everything from [[industrial electronics]] and [[measurement system]]s to [[hard disk]]s and networking equipment, among many other applications. Nowadays, synchronous SRAM (e.g. DDR SRAM) is rather employed similarly to synchronous DRAM{{snd}}[[DDR SDRAM]] memory is rather used than [[asynchronous DRAM]]. Synchronous memory interface is much faster as access time can be significantly reduced by employing [[pipeline (computing)|pipeline]] architecture. Furthermore, as DRAM is much cheaper than SRAM, SRAM is often replaced by DRAM, especially in the case when a large volume of data is required. SRAM memory is, however, much faster for random (not block / burst) access. Therefore, SRAM memory is mainly used for [[CPU cache]], small on-chip memory, [[FIFO (computing and electronics)|FIFO]]s or other small buffers.