Editing Processor design (section)

====Research and educational CPU design====
The 32-bit [[Berkeley RISC]] I and RISC II processors were mostly designed by a series of students as part of a four quarter sequence of graduate courses.<ref>{{cite web|url=http://www.eecs.berkeley.edu/Pubs/TechRpts/1982/CSD-82-106.pdf |archive-url=https://web.archive.org/web/20060305132258/http://www.eecs.berkeley.edu/Pubs/TechRpts/1982/CSD-82-106.pdf |archive-date=2006-03-05 |url-status=live|title=Design and Implementation of RISC I|author1=C.H. Séquin|author-link1=Carlo H. Sequin|author2=D.A. Patterson|author-link2=David A. Patterson (scientist)}}</ref>
This design became the basis of the commercial [[SPARC]] processor design.

For about a decade, every student taking the 6.004 class at MIT was part of a team—each team had one semester to design and build a simple 8 bit CPU out of [[7400 series]] [[integrated circuit]]s.
One team of 4 students designed and built a simple 32 bit CPU during that semester.<ref>{{cite web|url=http://sub-zero.mit.edu/fbyte/hacks/vhs/|title=the VHS|archive-url=https://web.archive.org/web/20100227055013/http://sub-zero.mit.edu/fbyte/hacks/vhs/|archive-date=2010-02-27}}
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Some undergraduate courses require a team of 2 to 5 students to design, implement, and test a simple CPU in a FPGA in a single 15-week semester.<ref>{{cite web|url=http://www.fpgacpu.org/teaching.html|title=Teaching Computer Design with FPGAs|author=Jan Gray}}</ref>

The MultiTitan CPU was designed with 2.5 man years of effort, which was considered "relatively little design effort" at the time.<ref>{{cite journal |last1=Jouppi |first1=N.P. |last2=Tang |first2=J.Y.-F. |title=A 20-MIPS sustained 32-bit CMOS microprocessor with high ratio of sustained to peak performance |journal=IEEE Journal of Solid-State Circuits |date=October 1989 |volume=24 |issue=5 |pages=1348–1359 |doi=10.1109/JSSC.1989.572612 |bibcode=1989IJSSC..24.1348J }}</ref>
24 people contributed to the 3.5 year MultiTitan research project, which included designing and building a prototype CPU.<ref>{{cite web|url=http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-87-8.pdf |archive-url=https://web.archive.org/web/20040825183403/http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-87-8.pdf |archive-date=2004-08-25 |url-status=live|title=MultiTitan: Four Architecture Papers|year=1988|pages=4–5}}</ref>